Seng Pan U, Ben余成斌
Visiting Professor

Academic Qualifications | Professional Experience | Honors and Awards | Student Honors and Awards under Advisory | Professional Services – Professional Associations and Institutions | Professional Services – Technical Committee and Conferences | Professional Activities | Invited Speeches & Technical Talks | Professional Affiliations | Teaching Experience | Thesis Supervision | Research Specialty | R&D Project Management Experience | Scientific Publications | Contact Details


Academic Qualification

  • Ph.D. in Electrical Engineering and Computer Science Engineering , Instituto Superior Técnico (IST), Universidade Técnica de Lisboa (UTL), Portugal (2004)
  • Ph.D. in Electrical and Electronics Engineering , Faculty of Science and Technology, University of Macau, China (2002)
  • M.Sc. in Electrical and Electronics Engineering , University of Macau (1997)
  • B.Sc. in Electronics Engineering , Jinan University, Canton, China (1991)

Professional Experience

Academic Working Experience

  • Professor, Dept. of EEE, FST, University of Macau (2011 – Present)
  • Deputy Director, The State Key Laboratory of Analog & Mixed-Signal VLSI, University of Macau (2011- Present)
  • Associate Professor , Dept. of EEE, FST, University of Macau (2005 – 2011)
  • Co-founder and Laboratory Coordinator, Analog & Mixed-Signal VLSI Research Laboratory, EEE/FST, University of Macau (2002 – 2010)
  • Assistant Professor , Dept. of EEE, FST, University of Macau (2002 – 2005)
  • Lecturer , Dept. of EEE, FST, University of Macau (1997 – 2002)
  • Visiting Researcher Fellow , Center of Microsystems, Instituto Superior Técnico, Universidade Técnica de Lisboa, Portugal (1999 – 2000)
  • Invited Lecturer, Short course on CMOS Analog Integrated Circuit Design – “Switched -Capacitor Circuit Techniques,” Athens Network of Higher Education, Instituto Superior Técnico/Universidade Técnica de Lisboa, Portugal (Jan.2000 – Feb.2000)
  • Visiting Scholar, Integrated Microsystems Laboratory, University of Pavia, Italy (Sep.1998 – Oct.1998)
  • Teaching Assistant , Dept. of EEE, FST, University of Macau (1994 – 1997)

Industrial Working Experience

  • General Manager and Senior Manager – Analog Design, Synopsys – Chipidea Microelectronics (Macau), Ltd. (2009 – Present)
  • Vice-President (IP Operations Asia Pacific) and General Manager, Chipidea Microelectronics (Macau), Ltd.(2003 – 2009)
  • Co-founder and Engineering Director, Chipidea Microelectronics (Macau), Ltd.(2001 – 2002)
  • Technical Support/Analyst , CEM (Companhia de Electricidade de Macau) (1993 -1994)
  • Electronics Engineer , PIC (Pacific Infotech Corporation) (1991 -1992)

Honors and Awards

2013   “2012 Outstanding Chapter Award” (Recipient as the Chapter Chair) awarded from IEEE Solid-State Circuits Society
2012   Second Class Award of the Macao Science and Technology Awards – Science and Technology Progress Award澳門科學技術獎勵科技進步獎二等獎(第一完成人),
awarded from Science and Technology Development Fund of Macao SAR (FDCT).
2012   Second Class Award of the Macao Science and Technology Awards – Technological Invention Award澳門科學技術獎勵技術發明獎二等獎(第二完成人),
awarded from Science and Technology Development Fund of Macao SAR (FDCT).
2011   Second Class Award of the State Scientific and Technological Progress Award 國家科學技術進步獎二等獎 (第一完成人) (澳門首獲 First from Macau)
The State Science and Technology Prizes (國家科學技術獎励) is the highest honor in China in science and technology, in order to recognize citizens and organizations who have made remarkable contributions to scientific and technological progress, and to promote the development of science and technology.
2010   Honorary Title of Value of 2010”, awarded by Macau SAR Government.
An annual government decoration for Macau citizen who has great contribution to Macau SAR reputation, development and society advancement.
2010   “HLHL Scientific and Technological Innovation Award” 何梁何利基金科學與技術創新獎 (澳門首獲 First from Macau) awarded from He Leung Ho Lee Foundation.
HLHL Scientific and Technology Prize is the highest level non-government annual award for its impact factor and authority in China science and technology society. The innovation award is to reward outstanding individuals who have attained remarkable R&D achievements in science and technology, have created businesses or famous brands with proprietary intellectual property through technology and management innovation, and thus have created enormous economic and social benefits for society.
2009   “IEEE CAS Chapter-of-the-Year Award” (Co-Recipient as Vice Chair of the Chapter) awarded from IEEE Circuits and Systems Society
2005   “Lecture Fellowship” awarded from K. C. Wong Education Foundation
2005   Nomination of “The 2005 National Best Doctoral Dissertations” from the Ministry of Education and State Academic Degrees Committee of the State Council.
2004   “FST Teaching Award 2004” awarded from University of Macau
2003   “Young Researcher Prize 2003” awarded from International Institute of Macau
2003   “The Most Favorite Teacher in 1st– and 2nd-year of EEE” awarded from Faculty of Science and Technology Students’ Association
2003   “The Most Favorite Teacher in 3rd– and 4th-year of EEE” awarded from Faculty of Science and Technology Students’ Association
2003   “The 2003 Chinese Expertise Dictionary” China.
2002   “The Most Favorite Teacher in EEE” awarded from Faculty of Science and Technology Students’ Association
2002   “Very Good with Honor and Distinction” awarded from University of Macau for Ph.D. degree (Highest honor)
2002   “The Outstanding Alumni Award” awarded from Hou Kong Middle School of Macau
2001   “Excellent Young Scholar Award 2001 (First Prize)” awarded from University of Macau.
2000   “Excellent Research Scholarship” from Center of Microsystems, Instituto Superior Técnico (IST), Universidade Técnica de Lisboa, Portugal
1999–2000   “Research Scholarship” from Fundação Oriente
1998   “Certificate of Merit” awarded from Institution of Electrical Engineers (IEE) for IEE (HK) Younger Members Section Paper Contest 97/98 (Postgraduate Session)
1998   “Certificate of Merit” awarded from Institute of Electrical and Electronic Engineers (IEEE) for 1998 IEEE Postgraduate Student Paper Contest (HK)
1997   “Very Good with Honor and Distinction” awarded from University of Macau for postgraduate study (Highest honor)
1991   “Excellent University Graduate Award” from Jinan University
1989–1991   “Excellent Student Scholarship” from Macau Higher Education Foundation
1987–1991   “Outstanding Student Scholarship” from Jinan University every semester
1990   “Province Outstanding University Scholar Award” awarded from the Guangdong Return Overseas Chinese Association

Student Honors and Awards under Advisory

Graduate Research

2012   “Travel Grant Award” awarded from 2012 IEEE Symposium on VLSI Circuits
Paper Title: Chi-Hang Chan, Yan Zhu, Sai Weng Sin, Seng Pan U, R. P. Martins, F. Maloberti, “A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure”
2012   2012 Best Master Thesis Award in Tsinghua University
Thesis Title: Guohe Yin,”满足生物医学低功耗需求的模数转换器设计技术研究”, Joint-Supervision with Tsinghua University
2011   Student Design Contest Award”, awarded from IEEE 2011 Asian Solid-State Circuits Conference (A-SSCC)
Paper Title: Yan Zhu, Chi-Hang Chan, Sai Weng Sin, Seng Pan U, R.P.Martins, Franco Maloberti, “A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation”
2011   Chipidea Microelectronics Prize, awarded from Chipidea Microelectronics, Macau
Paper title: Chi Hang Chan, “A Study on Comparator and Offset Calibration Techniques in High Speed Nyquist ADCs”
2011   2011 ISSCC Silk Road Paper Award” awarded from The 2011 International Solid-State Circuits Conference (ISSCC)
Paper Title:
He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins and F. Maloberti, “A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS”
2011   Bronze Leaf Certificate” awarded from The 2011 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia),
Paper Title: Yuan Fei, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “’A Nonlinearity Digital Background Calibration Algorithm for 2.5bit/stage Pipelined ADCs With Opamp Sharing Architecture”

2009

  Bronze Leaf Certificate” awarded from The 2009 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia),
Paper Title: U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Si-Seng Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Comparator-Based Successive Folding ADC,”

2006

  Merit Paper Award” awarded from The 2006 Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC)
Paper Title: Ka-Hou Ao Ieong, Seng-Pan U, Rui Paulo Martins, “Design of a 1-V 10-bit 120-MS/s Current-Steering DAC with Transient-Improved Technique”

2006

  Merit Paper Award” awarded from The 2006 Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC)
Paper Title: Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “Novel Timing-Skew-Insensitive, Multi-Phase Clock Generation Scheme For Parallel Dac And N-Path Filter”

2005

  Merit Paper Award” awarded from The 2005 Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC)
Paper Title: Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R. P. Martins, “On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC”

2005

  “Silver Leaf Certificate” awarded from The 2005 IEEE Ph.D. Research in Micro-Electronics & Electronics (PRIME)
Paper Title: Pui-In Mak, Seng-Pan U, R. P. Martins, “Multistandard-Compliant Receiver Architecture with low-voltage Implementation”

2005

  “2nd Place of Conceptual Category” awarded from IEEE DAC/ISSCC (Design Automation Conference/International Solid-State Circuit Conference) Student Design Contest
Paper Title: Pui-In Mak, Seng-Pan U, R.P.Martins, “A 1-V IEEE 802.11a/b/g-Compliant Receiver IF-to-Baseband Chip in 0.35-μm CMOS for Low–Cost Wireless SiP”

2005

  “Selected Student Paper Scholarship” awarded from IEEE International Symposium on Circuits and Systems (ISCAS)
Paper Title I: Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits”
Paper Title II: Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits”

2004

  “Best Paper Award” awarded in IEEJ (7th) International Analog VLSI Workshop (AVLSIWS 2004)
Paper Title: Pui-In Mak, Seng-Pan U, R.P.Martins, “A Power-and-Area Efficient, Multifunctional CMOS A/D Interface for a Low-IF/Zero-IF Reconfigurable Receiver”

2004

  “2nd Prize” in Student Paper Contest awarded from IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004)
Paper Title: Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R.P.Martins, “Modeling of Noise Sources in Reference Voltage Generator for Very-High-Speed Pipelined ADC”

Undergraduate Final Year Project

2012   2nd Runner-up for the Final Year Project Supervised: Zhao Tianxiang, “A Multibit Dual-Feedback CT Sigma Delta Modulator with Lowpass Signal Transfer Function”, 2012 IEEE Project Competition, Macau
2011  

1st Runner-Up for the Final Year Project Supervised: Yan PengYu, Chen Zhiyuan, “A 13-bit 64 MS/s Digital Enhanced Pipelined ADC for 4G LTE Application,” 2011 IEEE Project Competitions, Macau

2009

 

3rd-Prize for the Final Year Project Supervised: Jiang Yang, Yu Xiaofeng, Cai Chenyan, “A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers,” “Challenge Cup” National Intervarsity Science and Technology Competition, China

2009

 

Champion for the Final Year Project Supervised: Jiang Yang, Yu Xiaofeng, Cai Chenyan, “A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers,” 2009 IEEE Project Competitions, Macau

2008

 

Champion for the Final Year Project Supervised: Li Ding, Sio Chan, “A Pseudo-Differential Comparator-Based Pipelined ADC,” 2008 IEEE Project Competitions, Macau

2008

 

1st Runner-Up for the Final Year Project Supervised: Lei Chon Hei, “A Pseudo-Differential Comparator-Based Pipelined ADC,” 2008 IEEE Project Competitions, Macau

2008

 

1st Runner-up – Undergraduate Section for the Final Year Project Supervised: Li Ding, Sio Chan, “A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique,” IET Young Members Exhibition and Conference 2008, organized by Young members Section, IET(HK), Hong Kong, China

2004

  “3rd Prize” awarded from IEEE Macau Student Branch Project Competition’04
Project Title: Low-Voltage Sigma Delta Modulator With Reset-Opamp Technique for Portable Audio Data Acquisition System

2003

  “Outstanding Student Paper Award” awarded from The 5th International Conference on ASIC, Beijing, China
Paper Title: Pui-In Mak, Seng-Pan U, R.P. Martins, “A Programmable Switched-Capacitor A-DQS Frequency Downconverter for Two-Step Channel Selection Wireless Receiver”.

2003

  “1st Prize”, “Greatest Creativity Award”, “Greatest Practicability Award” awarded from IEEE Macau Student Branch Project Competition’03
Project Title: A Novel Zero-IF/Low-IF Reconfigurable Receiver for Multi-standard Wireless Communications

2003

  “1st Prize” awarded from The 8th “Challenging Cup” China National University Student Project Competition
『一等獎』中國第八屆挑戰杯全國大學生課外學術科技作品競賽
Project Title: A Novel Zero-IF/Low-IF Reconfigurable Receiver for Multi-standard Wireless Communications

Professional Services – Professional Associations and Institutions

  • Founding Chairman of IEEE SSCS Macau Chapter (2009 – Present)
  • Chairman of IEEE CAS/COMM Macau Chapter  (2008 – Present)
  • Member of Supervisory Committee of IEEE Macau Session (2006 – Present)
  • Industry Relationship Officer of IEEE Macau Session (2006 – Present)
  • Secretary of IEEE CAS/COMM Macau Chapter (2006 – 2007)
  • Nomination Committee Member for IEEE Macau Session Election Process of the Chief Officers for 2006-2007

Professional Services – Technical Committee and Conferences

  • Member of Evaluation Expert Panel of the National Science and Technology Awards國家科學技術獎勵評審專家
  • Technical Program Committee Member (Analog Circuits and Systems) of IEEE Asian Solid-State Circuits Conference (A-SSCC 2009, 2010, 2011,2012)
  • Technical Program Committee Member (Analog, Mixed-Signal & RF Design Subcommittee) of The 2013 International Symposium on VLSI Design, Automation and Test (2013 VLSI-DAT)
  • Editorial board member of Analog Integrated Circuits and Signal Processing, Springer
  • Technical Paper Review Committee of IEEE/IET Scientific Journal/ Transaction/Conferences: IEEE JSSC, IEEE TCAS-I/II, IEICE TElec, IET Electronics Letters, IEEE ISCAS (2002 – Present)
  • Sub-Committee Chair of Analog and Mixed-Signal Circuits and Systems, The 2011 IEEE International Symposium on Radio-Frequency Integration Technology – RFIT (2011)
  • Technical Program Co-Chair of The 2011 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia). (2011)
  • Panel member of Technical Assessment Committee of Transceiver chip for Implantable medical device (Swallowable Camera Pill), Institute of Microelectronics, Tsinghua University (2011)
  • Panel member of IIM Young Research Award from International Institute of Macau (2010)
  • Program Co-Chair of The 2009 International Conferences on Information, Communications and Signal Processing – ICICS’09, (2009)
  • Technical Program co-Chair of The 2008 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS’08), Nov. 30 – Dec. 3, Macau (2008)
  • Organization Chair of IEEJ International Analog VLSI Workshop (AVLSIWS 2004)

Professional Activities

2012   Co-Organizer of State Key Laboratory of Analog and Mixed-Signal VLSI – Science Series: Second Distinguished Lectures
Lecture 1: “The world of analog micro-power” by Prof. Franco Maloberti, Professor and Head of Micro Integrated Systems Group, University of Pavia, Italy, IEEE Fellow
Lecture 2:” Wearable Healthcare (Bio-Medical CMOS IC System Design) “by Prof. Hoi-Jun Yoo ,    professor and head of Semiconductor System Laboratory (SSL),Advanced Institute of Science and Technology (KAIST), Korea.
Lecture 3:” Low Power, High Bandwidth and Ultra-Small Memory Module Design” Prof. R. Jacob Baker, Boise State University, Boise-Idaho, USA, a joint academic and industrial training program, IEEE Life Fellow / IEEE Fellow / IEEE Senior Member
Lecture 4:” N-Path Filters”by Prof. Bram Nauta, Professor and Head of IC Design Group, University of Twente, The Netherlands, IEEE Fellow
Lecture 5: ” Low cost, high efficiency Power Management IC Design”, by Prof   Hong Zhiliang , Professor of Fudan University, China
Lecture 6: “Medical electronics – the next big engine for semiconductor industry” by Prof. Wang Zhihua, Tsinghua University,China
Lecture 7:” Talk 1: “Low energy and low voltage ADC design strategy” and Talk 2: “Proposing an interpolated pipeline ADC” by Prof. Akira Matsuzawa, Professor and Head of Matsuzawa and Okada Laboratories, Tokyo Institute of technology, Japan, IEEE Fellow
Lecture 8: ” What You Don’t Know About Miller Compensation” by Prof Chris Mangelsdorf, Analog Devices.
Lecture 9: “New Design Considerations on ESD Clamp Circuit in Nanoscale CMOS   Technology” by Prof. Ming-Dou Ker, Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan
2012   Organizer for The 2012 GSA (Global Semiconductor Association) – UM Semiconductor Insight Roundtable
Lecture 1:” China Semiconductor Industry: Growth and Opportunities” by Prof Xiaolang Yan, Professor of Zhejiang University, China
Lecture 2:” Smartphones: Hardware Platform, Software Development, Applications, and Education” by Prof. Tim Cheng, Professor of University of California, Santa Barbara,USA
Lecture 3:” Global Semiconductor Industry Outlook” by  Jeremy Wang, Asia-Pacific executive director, Global Semiconductor Association
Lecture 4:” An introduction to Super-K project of Peking University” by Prof. Xu Cheng, professor of  Peking University, China
Lecture 5:” Era of Customization and Specialization for Engery-Efficient Computing” by Prof. Jason Cong, Professor of University of California, Los Angela, USA
2012   Organizer for UM SKL Microelectronics Distinguished Lectures
Lecture 1:” Low-Power, High-Speed Smart Imagers and Vision Systems Using CMOS” by Prof. Ángel Rodríguez-Vázquez, Professor of University of Seville and Institute of Microelectronics of Seville.
Lecture 2:” Semiconductor Industry Trends, Challenges and Opportunities” by Dr. Rakesh Kumar, Vice President, IEEE Solid-State Circuits Society,President, TCX Inc.
Lecture 3:” The Next Wave of Mixed-Signal Interface Electronics” by Prof. Boris Murmann, Associate Professor and Head of Mixed Signal Integrated Circuit Design Group, Stanford University, USA
Lecture 4
:” Cryptography Hardware Implementation Issues” by Prof. Thanos Stouraitis, Professor of University of Patras ,President of IEEE circuits and system Society, / IEEE Fellow
2011   Special Session Organizer, “Power Efficient Data Converters” in The 2011 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
2011   Organizer of 30th UM Anniversary Distinguished Lectures on Microelectronics World-Leading Experts 2011 and SSCS DLP – State-of-the-Art Data Conversion and RF Technology in Nano CMOS, a joint academic and industrial training program
Lecture 1-2: “Mismatch-Shaping Techniques for Delta-Sigma Data Converters”, “Digital Background Calibration in Pipelined ADCs” by Prof. Ian Galton, Professor and Head of Integrated Signal Processing Group, University of California – San Diego, USA, IEEE Fellow
Lecture 3-4: “Ultra low-power & Wideband High-speed Nyquist AD converter” “RF circuit techniques in nanometer CMOS” by Prof. Bram Nauta, Professor and Head of IC Design Group, University of Twente, The Netherlands, IEEE Fellow
Lecture 5-6: “Analysis and Design of Switched-Capacitor Circuits”, “Digitally Assisted Data Converter Design” by Prof. Boris Murmann, Associate Professor and Head of Mixed Signal Integrated Circuit Design Group, Stanford University, USA
2008   Co-Organizer of Distinguished Lectures on Microelectronics World-Leading Experts 2008 – State-of-the-Art Data Conversion Technology in Nano CMOS, a joint academic and industrial training program
Lecture 1: “Recent Technology Trend of high Speed ADCs”, by Prof. Akira Matsuzawa, Professor and Head of Matsuzawa and Okada Laboratories, Tokyo Institute of technology, Japan, IEEE Fellow
Lecture 2: “Data Converters in the SOC Environment” by Prof. Bang-Sup Song, Professor and Charles Lee Powell Endowed Chair in Wireless Communication, University of California – San Diego, USA, IEEE Fellow
Lecture 3: ” Lower-Power Data Converters Design” by Prof. Franco Maloberti, Professor and Head of Micro Integrated Systems Group, University of Pavia, Italy, IEEE Fellow
2007   Organizer of Advanced Short Course of “Advanced Analog and Mixed-Signal CMOS Circuit Design”, by Prof. R. Jacob Baker, Boise State University, Boise-Idaho, USA, a joint academic and industrial training program
2007   Organizer of Distinguished Lectures on Microelectronics by World-Leading Experts 2007, a joint training academic and industrial training program
Lecture 1: “High Speed Op-amp Design: Compensation and Topologies for Two and Three Stage Designs”, by Prof. R. Jacob Baker, Boise State University, Boise-Idaho, USA
Lecture 2: “ESD Protection Design for Nanoelectronics” by Prof. Ming-Dou Ker, Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan
2007   Organizer of Short course of “Advanced ESD Protection Design for Nanoelectronics” by Prof. Ming-Dou Ker, Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan
2006   Co-Organizer of Distinguished Lectures on Microelectronics by World-Leading Experts 2006, a joint academic and industrial training program
Lecture 1: Minimizing Non-Idealities Due to Mismatch in Sub-Micron Analog CMOS Circuits Using Digital Calibration” by Prof. Ken Martin Stanley Ho Professor of Microelectronics, University of Toronto President, Snowbush Microelectronics, IEEE Fellow
Lecture 2: “On the Cutting Edge of Research Frontier in the Nanoelectronics Era – Human-Inspired Intelligent SoC and 20-100-GHz CMOS RF ICs” by Prof. Chung-Yu Wu, Chair Professor, at National Chiao Tung University, Adjunct International Professor, University of Illinois at Urbana-Champaign, IEEE Fellow, Fulbright Scholar
Lecture 3: “Technology Trends of Integrated Circuit in SoC based on the Analysis of ISSCC Papers” by Prof. Zhihua Wang, Professor and Executive Vice-Director of the Institute of Microelectronics, Tsinghua University, China
Lecture 4: ” Advanced Methodologies in Analog & Mixed Signal ICs Design ” by Prof. Dr. Zhiliang Hong, Deputy director of State Key Laboratory of ASIC & Systems, Fudan University, China

Invited Speeches & Technical Talks

Conference or Tutorial Talks

2013   SYNOPSYS Webinar, Apr 10, 2013
Topic: “What, Where, Who? Integrating Audio Analog Functionality into SoCs  – 如何将音频模拟功能集成进SoC”
2010   SYNOPSYS Webinar, Nov 23, 2010
Topic: “Tips for Embedding Flexible Analog Interface IP into Digital SoC’s for Broadband Communication – 灵活地将模拟接口IP嵌入宽带通信用数字SoC的技巧”
2010   SYNOPSYS Webinar, Jun 3, 2010
Topic: “Shaping the Perfect Audio Codec: How Your SoC Can Benefit from the Right Audio Functions’ Line-Ups – 打造完美的音频编解码器:让您的SoC从合适的音频功能产品组合中受益”
2007   Invited Tutorial Talk on The second IEEE International Workshop on Radio Frequency Integration Technology (RFIT), 9-11 Dec 2007, Singapore
Topic: Low-Voltage Analog Baseband Circuitry for Wireless Communication
2005   Invited Lecture in Tsinghua University, Fudan University and Zhejiang University, China
Topic 1: A Generalized Spectra Analysis of Sampled Signals with Timing-Mismatch Effects
Topic 2: Analog and Mixed-Signal ICs with Minimum Voltage Headroom – From Design Consideration to Implementation
2005   Invited Speech on IEEE Macau Student Branch Technology Seminar 2005
Topic: Integrated Circuit Technology Development: Historical Review and Prospective Future
2003   Invited Keynote Speech of The Symposium on Applied Science and Technology in Macau 2004 organized by The Association for Promotion of Science and Technology of Macau
Speech Topic: The development and Prospective Future of Microelectronics in Macau (澳門微電子發展之 “芯” 路歷程與展望)
2000   Invited Tutorial Talk for Short course on CMOS Analog Integrated Circuit Design – “Switched -Capacitor Circuit Techniques,” Athens Network of Higher Education, Instituto Superior Técnico/Universidade Técnica de Lisboa, Portugal

Local Invited Speeches

2012   Invited Speech:
Local Insertion in Macau Society – Microelectronics State Key Laboratory & Industry” by Prof . Seng-Pan U, General Manager and Senior Manager – Analog Design, Synopsys – Chipidea Microelectronics (Macau), Ltd; Visiting Professor of University of Macau
2012  

Invited Speech by University of Macau (UM) and the Science and Technology Development Fund (FDCT) of Macao SAR
Topic: “Macao Chip by Macao People” – Sharing Session on the First State Scientific and Technological Progress Award for Macao. 澳門人,澳門─澳門首獲國家科學技術進步獎成果分享會

2011   Invited Speech by The Macau Productivity and Technology Transfer Centre (CPTTM) for a workshop to Hunan Provincial Delegation Group of Science and Technology, P.R. China.  Jul. 26, 2011, Macau
Topic: Case Study: Development of Macau Microelectronics – from Academic R&D to Semiconductor Industry
2010   Invited Speech by Economic Services of the Government of the Macau, SAR for The 2010 Mainland, Hong Kong SAR and Macao SAR Intellectual Property Symposium, Oct. 27, 2010, Macau
Topic: Semiconductor IP – Enabling the Growth of Integrated Electronics
2010   Invited Scientific Seminar:『IEEE話你知-電機及電子在生活中的應用』, Jun 5, 2010
Topic: “微電子集成電路技術及其在澳門的發展”
2010   Invited Lecture of IET Week, Mar. 26, 2010
Topic: “Nano Integrated Circuit Technology and the Real Chips in Macau”
2009   Invited Distinguish Talk by APEMEM/IEEE Talk澳門機電工程專業協會(APEMEM)與澳門電機及電子工程師學會(IEEE), Dec. 11, 2009
Topic: “The Unfolding of Microelectronics in Macau – from Academic R&D to Semiconductor Analog IP Industry”
2009   Invited Talk of UM Career Talk, Feb. 2009
Topic: “Chipidea Microelectronics – World’s Leading Semiconductor IP Provider in Macau”,
2008   Invited Speech by Economic Services of the Government of the Macau, SAR for The 2008 Mainland, Hong Kong SAR and Macao SAR Intellectual Property Symposium, Nov. 25, 2008, Hong Kong
Topic: The Unfolding of the Analog Semiconductor IP Industry in Macau – from R&D to Market
2008   Seminar of Macau FDCT Research Press Conference, Jan. 2008
Topic: “Applied R&D for Advanced Microelectronics – Up to Full High-Definition, Multi-format Video Analog Front-End IP in 65nm CMOS: 高新微電子的應用研究–首片在65納米制程、達全高清的全制式視頻模擬前端系統知識產權”
2006   Invited Speech on Microelectronics Achievement Presentation for the Visit Prime Minister of Portugal
Topic: Microelectronics in Macau – From Desert to Oasis
2006   Invited Talk on “Chipidea 微電子“芯”系澳門”, Macau Young Job Fair, Jul, 2006
2003   Invited Speech of Macau Young Researcher Award of Institute International Macau (IIM), Nov. 2003
Speech Topic: Novel Multirate SC Interpolation Filtering Techniques for Very High-Speed Communications and Signal Processing

Professional Affiliations

  • Senior Member of The Institute of Electrical and Electronics Engineers (IEEE) (2005 – Present), Member (2000 – 2005), Student Member (1994 – 1999)
  • Member of The Macau Institute of Engineers (1994 – Present)

Teaching Experience

B.Sc. Courses

  1. System Design (ELEC437)
  2. Final Year Project (ELEC402)
  3. Circuit Analysis (ELEC231)
  4. Signals & Systems (ELEC261)
  5. Digital Signal Processing (ELEC370)

M.Sc. Courses

  1. Introduction to Research (IMSE001)
  2. Thesis (IMSE999)
  3. Microelectronics Circuit Design (IMSE004)
  4. Microelectronics for Telecommunication and Signal Processing (IMSE011)

Thesis Supervision

PH.D. Theses

  1. Chio U Fat (Alpha), Low-Power High-Speed ADC using Novel Two-Step Flash-SAR Architecture, 2012
  2. He-Gong Wei (Abner), Design techniques of High-Speed Low-power Small-Area Successive Approximation ADC, 2011
  3. Yan Zhu (Julia), Low-Power and High-Speed Reference-Free Successive Approximation Register ADCs, 2011
  4. Sin Sai Weng (Terry), Low-Voltage Very High-Speed Time-Interleaved Pipeline A-to-D Converter for Wideband Applications, 2007
  5. Mak Pui In (Elvis), Multistandard-Compliant and Low-Voltage Analog-Baseband Techniques for Wireless Communication Systems, 2006
  6. Arshad Hussain, The Design of Noise-Tolerant Passive Sigma-Delta ADC, On-going
  7. Zhong Jianyu (Jankey), Background Digital Calibration Techniques in Split-SAR ADC, On-going
  8. Li Ding, Digital Calibrated High-speed ADC , On-going
  9. Kim-Fai Wong (Vitor), Low Power SDM ADC, On-going
  10. Feng Da, Ultra Power Efficient Dynamic flash ADC, On-going
  11. Wong Si Seng (Dicky), Binary Search Algorithm and Digital Calibrated ADC, On-going
  12. Chan Chi Hang (Ivor), High Speed Power-Efficient Nyquist ADCs, On-going
  13. Zhongwu Zhao, High Speed Power-Efficient Nyquist ADCs, On-going

Master Theses

  1. Wong Si Seng (Dicky),Design of Analog-to-Digital Converters with Binary Search Algorithm andDigital Calibration Techniques, 2011
  2. Chan Chi Hang (Ivor), A Study on Comparator Offset Calibration Techniques and in High Speed Nyquist ADCs, 2011
  3. Li Ding,High-Performance Comparator-Based Pipelined Analog-to-Digital Converter, 2010
  4. Kim-Fai Wong,Fully-Differential Implementation of Comparator-Based Switched-Capacitor Circuits, 2010
  5. He-Gong Wei (Abner), High speed Analog-to-Digital Converter with high accurate Track-and-Hold circuit, 2008
  6. Yan Zhu (Julia), Comprehensive Linearity Analysis of High-Speed Power-Efficient Successive-Approximation ADCs with Series Capacitive DAC Structure, 2008
  7. Kin-Sang Chio (Sunny), A Robust Low-Distortion Sigma-Delta Modulator for Dual-Mode Wireless Receivers, 2007
  8. Kong Ngai (Nelson),Reconfigurable Switched-Current Fuzzy Logic Controller, 2007
  9. Ka-Hou Ao Ieong (Steven), Design of Low-Voltage Analog Baseband with Filter-Sharing for WLAN Transceivers, 2007
  10. Weng-Ieng Mok (Cherry), Characterizing and Solving Analog Impairment of Multi-Stage Analog-to-Digital Converter, 2007
  11. Ma Jun Xia (Meshell), Design of Power Efficient Flash-Interpolation Type ADC for UWB Applications, 2006
  12. Sin Sai Weng (Terry), A Timing-Jitter Noise Analysis for Time-Interleaved Sampled-Data Systems, 2003
  13. Lou Fan, Mismatch-Insensitive N-Path Multirate SC Sigma-Delta Modulator for High-Frequency Applications, 2002
  14. Yin Guohe, Ultra Low-Power SAR ADC for Biomedical Application, (Exchange student from Tsinghua University, Joint-Supervision with Prof. Zhihua Wang, Tsinghua University), On-going
  15. Wang Rui (Ray) , Digital Calibration Techniques for Cyclic Analog-to-Digital Converter, (Exchange student from Tsinghua University, Joint-Supervision with Prof. Zhihua Wang, Tsinghua University), On-going
  16. Chon-In Lao (Louis),Semi-MASH sigma-delta A-to-D Converter for high-speed high-resolution application, On-going
  17. Kin-Kwan Ma (Kobe),High-resolution Analog-to-Digital Converter for Video Application, On-going
  18. Kuai-Fok Au (Robert),Low-power, High Dynamic-Range Sigma-delta A-to-D Converter for Portable Audio System, On-going
  19. Yuan Fei (Frank),High-Resolution Pipeline ADC for video application, On-going
  20. Cheok-Teng_Lei (Tommy),Digital Calibration Technique for High-Resolution Pipeline ADC, On-going
  21. ChonHei_Lei (Franco),Digital Distortion Calibration using Dithering in Pipeline ADC, On-going
  22. Jiang Yang (Tim),Low-Power Circuits Techniques for Continuous-Time Sigma-Delta Analog-to-Digital Converter, On-going
  23. Cai Chenyan (Joy), Excess Loop Delay Compensation for Continuous-Time Sigma-Delta Analog-to-Digital Converter, On-going
  24. Zhang Peng, Power-Efficient Pipelined-SAR Analog-to-Digital Converter, (Exchange student from Tsinghua University, Joint-Supervision with Prof. Zhihua Wang, Tsinghua University), On-going
  25. Chen Zhijie, Ultra Low Power Sigma-Delta ADC for Biomedical Readout Front-End, (Exchange student from Tsinghua University, Joint-Supervision with Prof. Zhihua Wang, Tsinghua University), On-going
  26. Wu Wenlan, High-Resolution Low Power Pipelined ADC, On-going
  27. Du Yun, High-speed Continuous-Time Sigma-Delta Modulator, On-going
  28. He Tao,High-bandwidth Low Power Continuous-Time Sigma-Delta Modulator,  On-going

Bachelor Theses (total of 30, 1996 – 2011)


Research Specialty

  • CMOS Analog IC Design
  • Switched-Capacitor Circuits Design specialty
  • High-Performance Data-Converter Design
  • Analog Front-End for Communication & Consumer Electronic SoC

R&D Project Management Experience

Funded Research Projects

  1. “Research and Development of Comprehensive Data Conversion Platforms in Nanometer CMOS Technology,” funded by Macau Science and Technology Development Fund, 2010 – 2012   
  2. “Research and Development of Comprehensive Data Conversion Platforms in Nanometer CMOS Technology,” funded by Research Committee of University of Macau, 2010 – 2012
  3. “Integrated generalized PWM controller for DC-AC inverter,” funded by Research Committee of University of Macau, 2010 – 2012
  4. “High-Speed, High-Resolution, Low-Power Analog-to-Digital Conversion System with Emerging Scaled CMOS Technology,” funded by Macau Science and Technology Development Fund, 2007 – 2009
  5. “High-Speed, High-Resolution, Low-Power Analog-to-Digital Conversion System with Emerging Scaled CMOS Technology,” funded by Research Committee of University of Macau, 2007– 2009
  6. “Analog Baseband Microelectronics for SoC – Novel CMOS IF Data Conversion Platform For Multi-Standard Wireless Communication” funded from Research Committee of University of Macau, 2003 – 2006
  7. “Integrated Circuit Design of Low-Voltage Low-Power Multirate Analog-Digital System – LVLP/MADIC” funded from Research Committee of University of Macau, 1999 – 2001
  8. “Integrated Circuit Design Of Analog Impulse Sampled Interpolation (ISInt/IC)” funded from Fundação Oriente, 1999 – 2000

Industrial Engineering Projects

  1. “Research & Development of Advanced and Reusable Analog Front-End Semiconductor IP” funded by FDCT, 2006 – 2008
  2. Over 150 engineering projects developed for international IDMs, ASIC Manufactures, Fabless companies in the area of Audio/Voice Codec, Video Analog Front-End, WLAN/GSM Analog Front-End and other Communication or Consumer Electronics products, 2002 – present

Scientific Publications

Patents

  1. Sai-Weng SIN, He-Gong WEI, Franco MALOBERTI, Li DING, Yan ZHU, Chi-Hang CHAN , U-Fat    CHIO, Seng-Pan  U, Rui Paulo da Silva MARTINS” Analog to Digital Converter Circuit”, US Patent , US20120229313 A1, 13, Sep, 2012
  2. He-Gong WEI, U-Fat CHI, Sai-Weng SIN, Seng-Pan  U, Rui Paulo da Silva MARTINS,” Delay generator “US Patent ,US20120286840 A1, 15, Nov, 2012
  3. Yan ZHU, Chi-Hang CHAN , U-Fat CHIO, Sai-Weng SIN, Seng-Pan  U,Rui Paulo da Silva MARTINS, Franco MALOBERTI” bits successive approximation register analog-to-digital converting circuit” US Patent , US20120306679 A1, 6, Dec, 2012
  4. Ka-Hou AO IEONG, Seng-Pan U, “Single-ended to differential-ended converter by open loop based circuitry”, US Patent in application, 2011
  5. Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, R.P.Martins, F.Maloberti, “Two-Step Time-Interleaved SAR-ADC with Reused S&H,” Taiwan Patent in application, 2011.
  6. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “Flash-SAR Two-Step Subranging ADC,” Taiwan Patent in application, 2011.
  7. Sai-Weng Sin, Seng-Pan U and R. P. Martins, “Low-Voltage Finite-Gain Compensation Technique for High-Speed Reset- and Switched-Opamp Circuits,” US Patent in application, 2009.
  8. Sai-Weng Sin, Seng-Pan U and R. P. Martins, “Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits,” US Patent in application, 2009.
  9. Pui-In Mak, Seng-Pan U and R. P. Martins, “Switched Current-Resistor Programmable Gain Array for Low-Voltage Wireless LAN System and Method Using the Same,” US Patent, Pre-Grant Publication No. 2010/0184399, Jul. 2010.
  10. Pui-In Mak, Seng-Pan U and R. P. Martins, “Two-Step Channel Selection for Wireless Transmitter Front-Ends,” US Patent, Granted, No., Jun. 2011.
  11. Pui-In Mak, Seng-Pan U and R. P. Martins, “DC-Offset Canceled Programmable Gain Array for Low-Voltage Wireless LAN System and Method Using the Same,” US Patent, Granted, No. 7,948,309, May. 2011.
  12. Pui-In Mak, Seng-Pan U and R. P. Martins, “Two-Step Channel Selection for Wireless Receiver Front-Ends,” US Patent, Granted, No. 7,529,322, May 2009.

Book

  1. Seng-Pan U, R.P.Martins, J.E.Franca, “Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering,”, Springer, The Kluwer International Series in Engineering and Computer Science – Analog Circuits and Signal Processing, 2005. (ISBN: 978-0-387-26121-8)
  2. Seng-Pan U, R.P.Martins, J.E.Franca, “Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering,” China Science Press, The Oversea Electronics & Information Book Excellence Series, 2007 (ISBN: 978-7-03-018249-4).
  3. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters,” Springer 2010 (ISBN: 978-90-481-9709-5)
  4. Pui-In Mak, Seng-Pan U and R.P. Martins, “Analog-Baseband Architectures and Circuits – for Multistandard and Low-Voltage Wireless Transceivers,” Analog Circuits and Signal Processing, Springer, September 2007. (ISBN: 978-1-4020-6432-6)

Journal Papers

  1. He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti, “A 8-bit 400MS/s 2-bit per cycle SAR ADC with Resistive DAC”, IEEE Journal of Solid-State Circuits, vol. 47, Issue 11, pp. 2763-2772, Nov 2012. (ISSN : 0018-9200, SCI, EI, IF=3.226)
  2. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, “A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation”, IEEE Journal of Solid-State Circuits, vol. 47, Issue 11, pp. 2614 – 2626, Nov 2012. (ISSN : 0018-9200, SCI, EI, IF=3.226)
  3. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P. Martins and Franco Maloberti, “A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS,” in IEEE. Journal of Solid-State Circuits, vol. 45, issue 6, pp. 1111-1121, Jun. 2010. (ISSN :  0018-9200, SCI, EI, IF=3.47)
  4. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins and Franco Maloberti, “Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC,” in IEEE Trans. on Circuits and System II – Express Briefs, vol. 57, no. 8, pp. 607 – 611, Aug 2010. (ISSN :  1549-7747, SCI, EI, IF=1.44)
  5. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, “Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs,” in Hindawi VLSI Design, Special Issue “Selected Papers from the Midwest Symposium on Circuits and Systems”, vol. 2010, no. 1, pp. 1-8, Apr 2010, Invited. (ISSN :  1548-3746, Print ISBN: 978-1-4244-2166-4, EI)
  6. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS,” in IEEE Trans. on Circuits and System II – Express Briefs, vol. 57, no. 1, pp. 16-20, Jan 2010. (ISSN :  1549-7747, SCI, EI, IF=1.44)
  7. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 1.2-V 10-bit 60-360MS/s Time-Interleaved Pipelined ADC in 0.18um CMOS with Minimized Supply Headroom,” in IET Proceedings – Circuits, Devices and Systems, vol. 4, no. 1, pp. 1-13, Jan 2010. (ISSN :  1751-858X, SCI, EI, IF=0.52)
  8. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps,” in IEEE Transactions on Circuits and Systems I – Regular Papers, vol. 55, no. 8, Sep 2008. (ISSN :  1549-8328, SCI, EI, IF=2.04)
  9. Sai-Weng Sin, U-Fat Chio, Seng-Pan U and R. P. Martins, “Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch,” in IEEE Trans. on Circuits and Systems II – Express Briefs, vol. 55, no. 7, pp. 648 – 652, Jul 2008. (ISSN :  1549-7747, SCI, EI, IF=1.44, cited by: 1)
  10. Pui-In Mak, Seng-Pan U and R. P. Martins, “On the Design of Programmable-Gain Amplifier with Built-in Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems,” IEEE Transactions on Circuits and Systems – I: Regular Papers, vol. 55, no. 3, March, 2008. (ISSN :  1549-8328, SCI, EI, IF=2.04, cited by: 2)
  11. Pui-In Mak, Seng-Pan U and R. P. Martins, “An Experimental 1-V Flexible-IF CMOS Analogue-Baseband Chain for IEEE 802.11a/b/g WLAN Receivers,” IET Proceedings – Circuits, Devices and Systems, vol. 1, no. 6, pp. 415-426, Dec. 2007. (ISSN :  1751-858X, SCI, EI, IF=0.52)
  12. Pui-In Mak, Seng-Pan U and R. P. Martins, “Transceiver Architecture Selection – Review, State-of-the-Art Survey and Case Study,” IEEE Circuits and Systems Magazine, Vol. 7, Issue 2, pp. 6-25, Jun. 2007. (ISSN :  1531-636X, EI, cited by: 13)
  13. Pui-In Mak, Seng-Pan U and R.P.Martins, “Two-Step Channel Selection – A Novel Technique for Reconfigurable Multistandard Transceiver Front-Ends,” IEEE Transactions on Circuits and Systems-I, Regular Paper, vol.52, pp.1302-1315, Jul., 2005. (ISSN :  1549-8328, SCI, EI, cited by: 6)
  14. Seng-Pan U, Sai-Weng Sin and R.P.Martins, “Exact Spectra Analysis of Sampled Signals with Jitter-Induced Nonuniformly Holding Effects,” IEEE Transactions on Instrumentation and Measurement, vol. 53, pp. 1279-1299, Aug. 2004. (ISSN :  0018-9456, SCI, EI, cited by: 8)
  15. Seng-Pan U, R.P.Martins and J.E.Franca, “A 2.5-V 57-MHz 15-Tap SC Bandpass Interpolating Filter with 320-MHz Output for DDFS System in 0.35-µm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, No. 1, Jan. 2004. (Print ISBN: 0-7803-7335-9, SCI, EI)
  16. Pui-In Mak, Seng-Pan U and R.P.Martins, “Two-Step Channel Selection Technique by Programmable Digital-Double Quadrature Sampling for Complex Low-IF Receivers,” IEE Electronics Letters, vol. 39, no. 11, pp. 825-827, May 2003. (ISSN :  0013-5194, SCI, EI, cited by: 1)
  17. Seng-Pan U, R.P. Martins and J.E.Franca, “Improved Switched-Capacitor Interpolators with Reduced Sample-and-Hold Effects,” IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, vol.47, No.8, pp.665-684, Aug. 2000. (ISSN :  1057-7130, SCI, EI, cited by: 7)
  18. Seng-Pan U, R.P.Martins and J.E.Franca, “Offset-& Gain-Compensated and Mismatch-Free SC Delay Circuit with Flexible Implementation”, IEE Electronics Letters, vol. 35, No.3, pp.188-189, Feb. 4th. 1999. (ISSN :  0013-5194, SCI, EI)
  19. Seng-Pan U, R.P.Martins and J.E.Franca, “Impulse Sampled FIR Interpolation with SC Active-Delayed Block Polyphase Structures”, IEE Electronics Letters, vol. 34, No.5, pp.443-444, Mar. 5th. 1998. (ISSN :  0013-5194, SCI, EI, cited by: 3)
  20. Seng-Pan U, R.P.Martins and J.E.Franca, “Switched-Capacitor Interpolators Without the Input Sample-and-Hold Filtering Effect”, IEE Electronics Letters, vol. 32, No.10, pp.879-881, May 9th. 1996. (ISSN :  0013-5194, SCI, EI, cited by: 4)

Conference Papers

IEEE International Solid-State Circuits Conference ISSCC

  1. He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins and F. Maloberti, “A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS,” in IEEE International Solid-State Circuit Conference (ISSCC),  vol. 54, pp.188-189, Feb 2011. (ISSCC Silk Road Award)
  2. Seng-Pan U, R.P.Martins, J.E.Franca, “A 2.5 V, 57 MHz, 15-Tap SC Bandpass Interpolating Filter with 320 MHz Output Sampling Rate in 0.35mm CMOS,” IEEE International Solid State Circuits Conference (ISSCC) Digest of Technical Papers, pp.380-381/475, San Francisco, Feb. 2002.

IEEE Asian Solid-State Circuits Conference A-SSCC

  1. Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC”, IEEE Asian Solid-State Circuit Conference – (A-SSCC), Nov 2012.
  2. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U , R.P.Martins­ , Franco Maloberti, “A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation,” Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 61-64, Nov.2011.
  3. Si-Seng Wong,U-Fat Chio, He-Gong Wei, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A 4.8-bit ENOB 5-bit 500MS/s Binary-Search ADC with Minimized Number of Comparators,” Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 73-76, Nov.2011.
  4. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U , R.P.Martins, ” A Reconfigurable Low-Noise Dynamic Comparator with Offset Calibration in 90nm CMOS,” Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 233-236, Nov.2011.
  5. He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation,” in IEEE Asian Solid-State Circuit Conference (A-SSCC), paper no. 8-4 , Nov, 2010.
  6. Sai-Weng Sin, He-Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R.P. Martins and Franco Maloberti, ” On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator,” in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC), pp. 49-52, Nov 2009.

IEEE European Solid-State Circuits Conference ESSCIRC

  1. Guohe Yin, He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, R.P. Martins, “A 0.024mm2 4.9 fJ 10-Bit 2MS/s SAR ADC in 65 nm CMOS”, IEEE European Solid-State Circuits Conference – ESSCIRC 2012, pp. 377-380, Sept 2012.
  2. Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, “A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique”, IEEE European Solid-State Circuits Conference – ESSCIRC 2012, pp. 265-268, Sept 2012.
  3. U-Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration”, in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2011, pp. 363-366, Finland, September 2011.
  4. Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, R.P.Martins and F. Maloberti, “An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H”, in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010, Seville, Spain, September 2010.
  5. J.Risques, Seng-Pan U, Kuok Vai Chiang, Ka Fai Chang, Keng Chong Lai, Jorge Duarte, Vasco Amaro, “A Very Area/Power Efficient Mixed Signal Circuit For Voice Signal Processing In Pure 0.18 Digital Technology,” in Proc. IEEE European Solid State Circuits Conference 2003 – ESSCIRC’03 Portugal, Sep. 2003.

IEEE Symposium on VLSI Circuits VLSI

  1. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC”, 2012 Symposium on VLSI Circuits Digest of Technical Papers, page 90-91;13-15 June 2012, pp. 90-91, Jun 2012.
  2. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure”, 2012 Symposium on VLSI Circuits Digest of Technical Papers, page 86-87;13-15 June 2012, pp. 86-87, Jun 2012.
  3. Pui-In Mak, Seng-Pan U and R. P. Martins, “A 1V 14mW-per-Channel Flexible-IF CMOS Analog-Baseband IC for 802.11a/b/g Receivers,” IEEE Symposium on VLSI Circuits, Digest Technical papers (VLSI), pp.288-289, Jun. 2006.

IEEE Custom Integrated Circuits Conference CICC

  1. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC IEEE Custom Integrated Circuits Conference CICC 2012, Sept 2012.
  2. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC”, IEEE Custom Integrated Circuits Conference – CICC 2012, Sept 2012.
  3. Pui-In Mak, Seng-Pan U, R. P. Martins, “A 1-V Transient-Free and DC-Offset-Canceled PGA with a 17.1-MHz Constant Bandwidth over 52-dB Control Range in 0.35-µm CMOS,” in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 649-652, USA, Sep. 2005.

IEEE International Symposium on Circuits and Systems ISCAS

  1. Tao He, Yang Jiang, Yun Du, Sai-Weng Sin, Seng-Pan U and Rui.P. Martins, “A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer”, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 65-69, Korea, May 2012.
  2. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs”, in Proc. of 2010 IEEE International Symposium on Circuits and Systems (ISCAS),pp. 607-611, May. 2010.
  3. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, “A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier”, in Proc. of 2008 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5-8, Seattle, USA, May 2008.
  4. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R.P.Martins, “A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC,” to be appeared in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), USA, May 2007.
  5. Pui-In Mak, Seng-Pan U and R. P. Martins, “Design and Test Strategy underlying a Low-Voltage Analog-Baseband IC for 802.11a/b/g WLAN SiP Receivers,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp.2473-2476, Island of Kos, Greece, May 2006.
  6. Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Novel Low-Voltage Finite-Gain Compensation Technique for High-Speed Reset- and Switched-Opamp Circuits,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp.3794-3797, Greece, May 2006.
  7. Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A Power-Efficient 1.056 GS/s Resolution-Switchable 5-Bit/6-Bit Flash ADC for UWB Applications,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp.4305-4308, Greece, May 2006.
  8. Chon-In Lao, Seng-Pan U and R. P. Martins, “A Highly-Efficient Semi-Mash Structure for Bandpass Sigma-Delta Modulator with Double-Sampling Mismatch-Free Resonator,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS),  pp.581-584, Greece, May 2006.
  9. Kin-Sang Chio, Seng-Pan U and R. P. Martins, “A Dual-Mode Low-Distortion Sigma-Delta Modulator with Relaxing Comparator Accuracy,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp.1892-1895, Greece, May 2006.
  10. Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol.2, pp.1585-1588, Kobe, Japan, May 2005.
  11. Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol.2, pp.1581-1584, Kobe, Japan, May 2005.
  12. Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U and R.P.Martins, “A Frequency Up-Conversion and Two-Step Channel Selection Embedded CMOS D/A Interface,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.392-395, Kobe, Japan, May 2005.
  13. Chon-In Lao, Seng-Pan U and R.P.Martins, “High-order Cascade Sigma-Delta Modulator using Semi-MASH Sub-stage,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.3095-3098,Kobe, Japan, May 2005.
  14. Kin-Sang Chio, Seng-Pan U and R.P.Martins, “A Robust 3rd Order Low-Distortion Multi-bit Sigma-Delta Modulator with Reduced Number of Op-amp Technique for WCDMA,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.3099-3102, Kobe, Japan, May 2005.
  15. Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems,” in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), vol.1, pp. I-369 – I-372 , May 2004.
  16. Pui-In Mak, Seng-Pan U, R.P.Martins, “A Low-IF/Zero-IF Reconfigurable Receiver with Two-Step Channel Selection Technique for Multistandard Applications,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.417-420, Vancouver, Canada, May 2004.
  17. Pui-In Mak, Kin-Kwan Ma, Weng-Ieng Mok, Chi-Sam Sou, Kit-Man Ho, Cheng-Man Ng, Seng-Pan U, R.P.Martins, “An I/Q-Multiplexed and Op-Amp-Shared CMOS Pipelined ADC with an A-DQS S/H Front-End for Two-Step-Channel-Select Low-IF Receiver,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.1068-1071, Vancouver, Canada, May 2004.
  18. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Timing-Mismatch Analysis in High-Speed Analog Front-End with Nonuniformly Holding Output,” in Proc. of IEEE International Symposium on Circuits and Systems 2003 – “ISCAS’2003, Bangkok, Thailand, May 2003.
  19. Chon-In Lao, Ho-Ieng Ieong, Kuai-Fok Au, Kuok-Hang Mok, Seng-Pan U, R.P.Martins, “A 10.7-MHz Bandpass Sigma-Delta Modulator using Double-Delay Single-Opamp SC Resonator with Double-Sampling,” in Proc. of IEEE International Symposium on Circuits and Systems 2003 – “ISCAS’2003, Bangkok, Thailand, May 2003.
  20. Seng-Pan U, R.P.Martins,  J.E.Franca, “Design and Analysis of Low Timing-Skew Clock Generation for Time-Interleaved Sampled-Data Systems,” in Proc. of IEEE International Symposium on Circuits and Systems 2002 – “ISCAS’2002, Volume IV, pp. 441-444, Scottsdale, Arizona, U.S.A., May 2002.
  21. Seng-Pan U, R.P.Martins, J.E.Franca, “A High-Speed Frequency Up-Translated SC Bandpass Filter With Auto-Zeroing For DDFS Systems,” in Proc. of The 2001 IEEE International Symposium on Circuits and Systems (ISCAS’2001), Volume. I, pp.320-323, Sydney, Australia, May 2001.
  22. Seng-Pan U, R.P.Martins, J.E.Franca, “High-Frequency Low-Power Multirate SC Realizations For NTSC/PAL Digital Video Filtering,” in Proc. of The 2001 IEEE International Symposium on Circuits and Systems (ISCAS’2001), Volume. I, pp.204-207, Sydney, Australia, May, 2001.
  23. Seng-Pan U, R.P.Martins, J.E.Franca, “A Linear-Phase Halfband SC Video Interpolation Filter With Coefficient-Sharing And Gain- & Offset-Compensation,” in Proc. of The 2000 IEEE International Symposium on Circuits and Systems (ISCAS’2000), Volume. III, pp.177-180, Geneva, Switzerland, May 28-31, 2000.
  24. Seng-Pan U, R.P.Martins, J.E.Franca, “Highly Accurate Mismatch-Free SC Delay Circuits With Reduced Finite Gain And Offset Sensitivity,” in Proc. of 1999 IEEE International Symposium on Circuits and Systems (ISCAS’99), Volume.2, pp.57-60, USA, May 1999.
  25. Seng-Pan U, R.P.Martins, J.E.Franca, “High Performance Multirate SC Circuits With Predictive Correlated Double Sampling Technique,” in Proc. of 1999 IEEE International Symposium on Circuits and Systems (ISCAS’99), Volume.2, pp.77-80, USA, May 1999.
  26. Seng-Pan U, R.P.Martins, J.E.Franca, “Intermittent Polyphase SC Structures for FIR Rational Interpolation,” in Proc. of IEEE International Symposium on Circuits and Systems 1997 – “ISCAS’1997, Volume.I, pp.121-124, Hong Kong, Jun 1997.

IEEE International Conference on Electronics, Circuits and Systems ICECS

  1. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 547-550, Dec, 2010.
  2. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 547-550, Dec, 2010.
  3. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, “A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs,” in Proc. of 2008 IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 642-645, Aug 2008.
  4. Pui-In Mak, Seng-Pan U, R.P. Martins, “A Front-to-Back-end Modeling of I/Q Mismatch Effects in a Complex-IF receiver for large image-rejection,” in Proc. of IEEE International Conference of Electronics, Circuits and Systems (ICECS’ 2003), pp. 631-634, Sharjah, United Arab Emirates, 2003.
  5. Pui-In Mak, Chi-Sam Sou, Seng-Pan U, R.P. Martins, “Frequency-Downconversion and Channel Selection Sample-and-Hold circuit with A-DQS technique for Complex Low-IF Wireless Receivers,” in Proc. of IEEE International Conference of Electronics, Circuits and Systems (ICECS’2003), pp. 479-482, Sharjah, United Arab Emirates, 2003.
  6. Fan Lou, Seng-Pan U, R.P.Martins, “N-Path Multirate Sigma-Delta Modulator For High Frequency Application,” in Proc. of The IEEE International Conference on Electronics, Circuits and Systems (ICECS’2002) pp.315-318, Sep. 2002.
  7. Seng-Pan U, R.P.Martins, J.E.Franca, “A Novel Half-Band SC Architecture for Effective Analog Impulse Sampled Interpolation,” in Proc. of The 5th IEEE International Conference on Electronics, Circuits and Systems-ICECS’98, pp.389-403, Lisbon, Portugal, Sep. 1998.
  8. Seng-Pan U, R.P.Martins, J.E.Franca, “New Impulse Sampled IIR Switched-Capacitor Interpolators,” in Proc. of The Third IEEE International Conference on Electronics, Circuits and Systems (ICECS’96), pp.203-206, Rodos, Greece, Oct. 1996.

IEEE Midwest Symposium on Circuits and Systems MWSCAS

  1. Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U R.P. Martins, “An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators”, IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), 2012, Aug 2012
  2. Yang Jiang, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “Clock-Jitter Sensitivity Reduction in CT ΣΔ Modulators Using Voltage-Crossing Detection DAC,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  3. Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U and Rui. P. Martins, “A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time ΣΔ Modulators,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  4. Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  5. Peng Zhang, Zhijie Chen, He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Zhihua Wang, “A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  6. Zhijie Chen, Peng Zhang, Hegong Wei, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Zhihua Wang, “Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  7. Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A Multi-Merged-Switched Redundant Capcitive DACs for 2b/cycle SAR ADC,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  8. Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Threshold-Embedded Offset Calibration Technique for Inverter-Based Flash ADCs,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 489-492, August 2010.
  9. Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Level-Shifting Variable Current Charging Technique for High-Speed Comparator-Based Switched-Capacitor Circuits,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, , pp. 566-569, August 2010.
  10. Si-Seng Wong, U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Power Effective 5-bit 600 MS/s Binary-Search ADC with Simplified Switching,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 29-32 August 2010.
  11. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 889-892 August 2010.
  12. Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U and R.P. Martins, ” A Modified Charging Algorithm for Comparator-Based Switched-Capacitor Circuits,” in Proc. of 2009 Midwest Symposium on Circuits and Systems (MWSCAS), pp. 86-89, Aug. 2009.
  13. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, ” Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs,” in Proc. of 2008 Midwest Symposium on Circuits and Systems (MWSCAS), pp. 922-925, Aug 2008 .
  14. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R.P.Martins, “Modeling of Noise Sources in Reference bVoltage Generator for Very-High-Speed Pipelined ADC,” in Proc. of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), vol.1 , pp. 5-8, Hiroshima, Japan, July 2004.
    (2nd Prize, MWSCAS Student Paper Contest)
  15. Fan Lou, Seng-Pan U, R.P.Martins, “Mismatch-insensitive N-Path Multirate Sigma-Delta Modulator for High-Frequency Applications,” in Proc. of The 45th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’2002), Aug. 2002.
  16. Seng-Pan U, R.P.Martins, J.E.Franca, “Impulse Sampled Intermittent SC FIR Rational Decimators With Double-Sampling,” in Proc. of 1997 IEEE 40th Midwest Symposium on Circuits and Systems, pp.977-980, Sacramento, USA, Aug. 1997.
  17. Seng-Pan U, R.P.Martins, J.E.Franca, “Switched-Capacitor Finite Impulse Response Interpolators Without the Input Sample-and-Hold Filtering Effect,” inProc. of 1996 IEEE 39th Midwest Symposium on Circuits and Systems, Ames, Iowa, USA, Aug. 1996.

IEEE Asia-Pacific Conference on Circuits and Systems APCCAS

  1. Zhijie Chen, Yang Jiang, Chenyan Cai, He-Gong Wei, Sai-Wen Sin, Seng-Peng U, Zhihua Wang, R. P. Martins, “A 22.4µW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012.
  2. Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A Robust NTF Zero Optimization Technique for Both Low and High OSRs Sigma-Delta Modulators”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012.
  3. Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012.
  4. Wen-Lan Wu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array”, IEEE ASIA Pacific Conference on Circuits and system (APCCAS), 2012.
  5. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1011-1014, Dec. 2010.
  6. Li Ding, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 208-211, Dec. 2010.
  7. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, ” A Process- and Temperature- insensitive Current-Controlled Delay Generator for Sampled-Data Systems,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1192-1195, Dec. 2008.
  8. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, ” A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1164-1167, Dec. 2008.
  9. Li Ding, Sio Chan, Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U and R.P. Martins, ” A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feed Forward Technique” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 276-279, Dec. 2008.
  10. Ka-Hou Ao Ieong, Seng-Pan U and R. P. Martins, “A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique,” to be appeared in The Proceeding of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2006.

IEEE Instrumentation and Measurement Technology Conference IMTC

  1. Seng-Pan U, Sai-Weng Sin, R.P.Martins, “Spectra Analysis of Nonuniformly Holding Signals for Time-Interleaved Systems with Timing Mismatches,” in IEEE Instrumentation and Measurement Technology Conference – IMTC’2003, Vail, Colorado, U.S.A., pp. 1298-1301, May 2003.

IEEE International Conference on Acoustics, Speech & Signal Processing ICASSP

  1. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Quantitative Noise Analysis of Jitter-Induced Non-Uniformly Sampled-And-Held Signals,” in IEEE International Conference on Acoustics, Speech and Signal Processing – “ICASSP’2003″, Hong Kong, China, pp.VI-253-256, April 2003.

IEEE International Conference on ASIC ASICON

  1. Pui-In Mak, Seng-Pan U, R.P. Martins, “A Programmable Switched-Capacitor A-DQS Frequency Downconverter for Two-Step Channel Selection Wireless Receiver,” in Proc. of IEEE International Conference on ASIC – ASICON’2003, pp.573-576, Beijing, China, Oct. 2003.
    (Outstanding Student Paper Award)
  2. Chon-In Lao, Seng-Pan U, R.P.Martins,  “Bandpass Sigma-Delta Modulator SIMULINK® Non-Idealities Model with Behavior Simulation,” in Proc. of IEEE International Conference on ASIC – ASICON’2003, pp.685-688, Beijing, China, Oct. 2003.
  3. Seng-Pan U, Ho-Ming Cheong, Iu-Leong Chan, Keng-Meng Chan, U-Chun Chan, Mantou Liu, R.P.Martins, J.E.Franca, “An SC CCIR-601 Video Restitution Filter With 13.5 Msample/S Input and 108 Msample/S Output,” in Proc. of IEEE International Conference on ASIC – ASICON’2001, pp.374-377, Shanghai, China, Oct. 2001.

IEEE International Symposium on Radio-Frequency Integration Technology RFIT

  1. Seng-Pan U, Sai-Weng Sin, Yan Zhu, U-Fat Chio, He-Gong Wei and, R. P. Martins, “Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs,” in Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011, pp. 173-176, Beijing, China, Nov. 2011.

IEEJ International Analog VLSI Workshop – AVLSIWS

  1. Pui-In Mak, Seng-Pan U, R.P.Martins, “A Power-and-Area Efficient, Multifunctional CMOS A/D Interface for a Low-IF/Zero-IF Reconfigurable Receiver,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 233-238, Macao, China, Oct. 2004.
    (Best Paper Award)
  2. Pui-In Mak, Ka-Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R.P.Martins, “A Complex Low-IF Transceiver Architecture for Relaxing Phase Noise and Settling Time Requirements of RF PLL-FS,” in Proc. of IEEJ (7th) International Analog VLSI Workshop, pp. 221-226, Macao, China, Oct. 2004.
  3. Hon-Weng Chong, Kai-Yiu Che, Seng-Pan U, R.P.Martins, “A 1-V 2.56-MHz Clock-Rate CMOS Multi-bit Sigma-Delta Modulator with Reset-Opamp Technique and Pseudo Data-Wwighted-Averaging for Portable Audio Data Acquistion,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 180-185, Macau SAR, China, October 2004.
  4. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R.P.Martins, “Model, Characterization and Solutions of Unstable Reference Voltage for Very-High-Speed Pipelined A/D Converters,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 138-143, Macau SAR, China, October 2004.
  5. Kai-Yiu Che, Hon-Weng Chong, Seng-Pan U, R.P.Martins, “A 1-V 5.12-MHz Sampling-Rate 13-bit CMOS Sigma-Delta Modulator Using Reset-Opamp Technique for Portable Aduio Data Acquistion System,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 186-191, Macau SAR, China, October 2004.
  6. Ka-Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R.P.Martins, “A Multistandard Transmitter D/A Interface with Embedded Frequency Up-Conversion and Two-Step Channel Selection,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 215-220, Macau, China, Oct. 2004.

China Association Science and Technology Conference of Young Scientists CAST

  1. Seng-Pan U, “A Novel Frequency-Translated Filtering Technique for DDFS Systems and its Integrated Circuit Implementation,” Proc. of The 4th China Association Science and Technology (CAST) Conference of Young Scientists, pp.46-47, Beijing, China, Oct. 2001 (in Chinese).
  2. Seng-Pan U, “A Novel Impulse Sampled Interpolation Technique for Efficient and Accurate Analog Multirate Signal Processing,” in Proc. of The 3rd China Association for Science and Technology (CAST) Conference of Young Scientists, Beijing, China, Aug. 1998 (in Chinese).

Other International Conference

  1. Arshad Hussain, Sai-Weng Sin, Seng-Pan U, Rui P. Martins, “Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation”, International SoC Design Conference – ISOCC, pp. 76-79, Nov 2011
  2. Arshad Hussain, Sai-Weng Sin, Seng-Pan U, Rui P. Martins, “NTF Zero Compensation Technique For Passive Sigma-Delta Modulator”, IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 82-851, Oct 2011
  3. Yuan Fei, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A Nonlinearity Digital Background Calibration Algorithm for 2.5bit/stage Pipelined ADCs With Opamp Sharing Architecture”, IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 1-4, Oct 2011.
  4. Rui Wang, U-Fat Chio, Chi-Hang Chan, Li Ding, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, “A time-efficient dither-injection scheme for pipelined SAR ADC”, IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 9-12, Oct 2011
  5. Bo Sun, U-Fat Chio, Chi-Seng Lam, Ning-Yi Dai, Man-Chung Wong, Chi-Kong Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A FPGA-Based Power Electronics Controller for Hybrid Active Power Filters”, IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 25-28, Oct 2011
  6. Bo Sun, Ning-Yi Dai, U-Fat Chio, Man-Chung Wong, Chi-Kong Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “FPGA-based Decoupled Double Synchronous Reference Frame PLL for Active Power Filters”, 2011 6th IEEE Conference on Industrial Electronics and Applications (ICIEA), pp. 2145 – 2150, 2011
  7. Yuan Fei, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Digital Background Nonlinearity Calibration Algorithm for Pipelined ADCs,” IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), 2010.
  8. Si-Seng Wong, Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs,” in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 333-336, Nov. 2009.
  9. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator,” in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 392-395, Nov. 2009.
  10. Cheok-Teng Lei, Seng-Pan U and R. P. Martins, “High-Speed Robust Level Converter for Ultra-Low Power 0.6-V LSIs to 3.3-V I/O,” in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 396-399, Nov. 2009.
  11. U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Si-Seng Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Comparator-Based Successive Folding ADC,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pp. 117-120, Nov. 2009.
    (Bronze Leaf Certificate)
  12. Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “Novel Timing-Skew-Insensitive, Multi-Phase Clock Generation Scheme For Parallel Dac And N-Path Filter,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 32, Macau, Jul. 2006.
  13. Ka-Hou Ao Ieong, Seng-Pan U, Rui Paulo Martins, “Design of a 1-V 10-bit 120-MS/s Current-Steering DAC with Transient-Improved Technique,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 33, Macau, Jul. 2006.
  14. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R. P. Martins, “A Novel Architecture of Comparator-Mismatch-Free Multi-Bit Pipeline ADC,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 31, Macau, Jul. 2006.
  15. Chon-In Lao, Seng-Pan U, R. P. Martins, “A Expandable and Extendable High-order Semi-MASH Sigma-Delta Modulator,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 15, Macau, Jul. 2006.
  16. Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “1.8-V 1.056-Gs/S 6-B Flash-Interpolation ADC For Mb-Ofdm Uwb Applications,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 25, Macau, Jul. 2006.
  17. Ngai Kong, Seng-Pan U, R. P. Martins, “A Novel Current-Mode Reconfigurable Memebership Function Circuti For Mixed-Signal Fuzzy Hardware,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 24, Macau, Jul. 2006.
  18. Pui-In Mak, Seng-Pan U, R. P. Martins, “Multistandard-Compliant Receiver Architecture with low-voltage Implementation,” in Proceedings of Ph.D. Research In Micro-Electronics & Electronics (PRIME), pp. 223-226, Lausanne, Switzerland, Jul. 2005. (Silver Leaf Certificate)
  19. Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Novel low-voltage circuit techniques for fully-differential reset- and switched-opamps,” in Proceedings of Ph.D. Research In Micro-Electronics & Electronics (PRIME), Switzerland, pp. 398-401, Lausanne, Switzerland, Jul. 2005.
  20. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R. P. Martins, “On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC,” in Proceedings of Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC), pp. 276-280, Hong Kong, China, Jun. 2005.
  21. Kin-Sang Chio, Seng-Pan U, R.P.Martins, “A novel low-voltage 2nd-order sigma-delta modulator with double-sampling for GSM/DECT/WCDMA,” in Proc. of International Conference on Communications, Circuits and Systems (ICCCAS), pp. 1146-1150, vol. 2, Jun. 2004.
  22. Pui-In Mak, Weng-Ieng Mok, Seng-Pan U, R.P. Martins, “I/Q Imbalance Modeling of Quadrature Transceiver Analog Front-Ends in SIMULINK,” in Proc. of the 58th IEEE International Conference on Vehicular Technology, pp. 2371-2374, Orlando, Florida, USA. Oct. 2003.
  23. Pui-In Mak, Seng-Pan U, R.P. Martins, “A Novel IF channel Selection Technique by Analog- Double quadrature Sampling for Complex low-IF receivers,” in Proc. of IEEE International Conference of Communication Technology, pp.1238-1241, Beijing, China, Apr.2003.
  24. Seng-Pan U, R.P.Martins, J.E.Franca, “Experimental Results of SC Fractional Multirate Converters with Intermittent Polyphase Structures,” in Proc. Of The First Portugal-China Workshop on Solid-State Circuits, pp.28-29, Shanghai, China. Oct. 25-27, 2000.
  25. Seng-Pan U, R.P.Martins, J.E.Franca, “A 120 MHz SC 4th-Order Elliptic Interpolation Filter with Accurate Gain and Offset Compensation For Direct Digital Frequency Synthesizer,” in Proc. of The First IEEE Asia-Pacific Conference on ASICs (AP-ASIC’99), pp.1-4, Korea, Aug. 1999.
  26. Guohe Yin, He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, Rui Paulo Martins, ” A 0.014mm2 4.8fJ/step 10-bit 1-MS/s SAR ADC for Bio-medical Applications,” to be submitted.

Macau Local Journals

  1. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18um CMOS”, 澳門機電工程專業協會(APEMEM)會刊(2007-2008), pp. 37-43.
  2. U Seng Pan, R.P.Martins, J.E.Franca, “A 2.5V 320MSample/S SC Bandpass Multirate Filter for DDFS System in 0.35um CMOS,” in Proc. Symposium On Technological Innovation In Macau, Macau, China, Dec. 2002.
  3. U Seng Pan, R.P.Martins, J.E.Franca, “New Impulse Sampled Switched-Capacitor Interpolators” in Macau Engineering Bulletin, No. 3, Dec. 1996

Contact Details

Faculty of Science and Technology
University of Macau, E11
Avenida da Universidade, Taipa,
Macau, China

Room: —
Telephone: (853) 8822-4376
Fax: (853) 8397-8797
Email: benspu