UM research wins CICC Outstanding Regular Paper Award
澳大研究獲CICC最佳論文獎

A research group led by Associate Professor Mo Huang in the Institute of Microelectronics (IME) at the University of Macau (UM) has been awarded the Outstanding Regular Paper Award at the 2025 IEEE Custom Integrated Circuits Conference (CICC) for their research on a continuously scalable-conversion-ratio switched-capacitor (SC) converter (CSCR) based on only four flying capacitors. Notably, it was the only paper to receive the Outstanding Regular Paper Award at the conference. The paper has also been invited for publication in the IEEE Journal of Solid-State Circuits (JSSC) and has been shortlisted for the ‘Top 10 Semiconductor Research Advances’ by the Journal of Semiconductors (English Edition). This marks the first time UM has received an Outstanding Regular Paper Award at CICC, reflecting the growing international recognition of the university’s research excellence in analogue and mixed-signal integrated circuits.

There is a pressing demand for high efficiency, high density power delivery in data centres. However, traditional inductor-based converters suffer from low power density, while switched-capacitor converters, though denser, struggle to maintain high efficiency across a wide voltage range. Intel’s previously proposed CSCR architecture requires over 30 capacitors, resulting in high costs and a strong reliance on advanced process technologies. Prof Huang and his research team have achieved a breakthrough with an ultra-compact hybrid CSCR architecture featuring three key innovations: (1) a front end switched-capacitor stage that clamps the flying capacitor voltage swing to one quarter of its original value, substantially reducing charge sharing losses; (2) a half-outphasing technique that sustains high efficiency across a wide conversion ratio range using only four flying capacitors; and (3) a stage outphasing technique that further optimises overall efficiency.

Measurements show peak efficiency of 92.5% and maximum single-phase output power of 1.52 W. Compared with Intel’s architecture, the new design reduces the number of flying capacitors by 70%, the number of switches by 80%, and the switch idle ratio by 50%, all achieved without relying on high-density on-chip capacitors. These improvements significantly lower process barriers and costs, and facilitate commercialisation. The research redefines the design methodology for CSCRs, breaking the conventional notion that high efficiency must come at the cost of high resource consumption. The proposed technology can be extended to 2.5D/3D advanced packaging and is particularly well suited for point-of-load power delivery in data centres and edge computing.

The corresponding author of the study is Prof Huang. The first author is Wang Yuanfei, a postdoctoral fellow in IME. The co-authors are Rui Martins, vice rector of UM and director of IME; and PhD student Zhang Zhiyuan and master’s student Zhong Ziyang in IME. Zhang Yihan, assistant professor in the School of Engineering at The Hong Kong University of Science and Technology, also contributed to the study. The research was funded by the Science and Technology Development Fund of the Macao SAR (Grant Nos.: 0041/2022/A1 and 004/2023/SKL). The full version of the research article is available at: https://ieeexplore.ieee.org/abstract/document/10983039.

Source: Institute of Microelectronics