Sai Weng SIN, Terry冼世榮
Associate Professor
Associate Head of Department of Electrical and Computer Engineering (ECE)

Academic Qualifications | Professional Experience | Teaching Experience | Research | Professional Services – External | Professional Services – Internal | University Student Life and Development Service | Professional Review Services | Honors and Awards | Student Honors and Awards under Advisory | Invited Talks | Scientific Publications | Professional Affiliations | Contact Details


Academic Qualification

  • Ph.D. in Electrical and Electronics Engineering, Faculty of Science and Technology, University of Macau, China (2008)
  • M.Sc. in Electrical and Electronics Engineering, Faculty of Science and Technology, University of Macau, China (2003)
  • B.Sc. in Electrical and Electronics Engineering, Faculty of Science and Technology, University of Macau, China (2001)

Professional Experience

  • Associate Head, Dept. of ECE, FST, University of Macau (2016 Nov – present)
  • Associate Professor, Dept. of ECE, FST, University of Macau (2015 – present)
  • Assistant Professor, Dept. of ECE, FST, University of Macau (2009 – 2015)
  • Academic Coordinator, State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau (2014 – Present)
  • Coordinator, Data and Power Conversion (DP) Innovation Research Center, State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau (2017 – Present)
  • Coordinator, Data Conversion and Signal Processing (DCSP) Research Line, State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau (2007 – 2017)
  • Co-Coordinator, Integrated Power Research Line, State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau (2007 – 2017)
  • Post-Doctoral Fellow, Analog and Mixed-Signal VLSI Laboratory, Dept. of EEE, FST, University of Macau (2008 –2009)
  • Senior Research Assistant, Analog and Mixed-Signal VLSI Laboratory, Dept. of EEE, FST, University of Macau (2007 –2008)

Teaching Experience

B.Sc. Courses

  1. Analog Integrated Circuit Design (ELEC371)
  2. Signals and Systems (ECEB210 / ELEC261)
  3. System Design (ELEC437) / Design Project I (ECEB410)
  4. Project (ELEC402) / Design Project II (ECEB420)

M.Sc. Courses

  1. Advanced Topics in Analog and Mixed-Signal Integrated Circuits (IMSE022/ELCE722)
  2. Microelectronic Circuit Design (IMSE004)
  3. Microelectronic for Telecommunication and Signal Processing (IMSE011/ELCE711)
  4. Introduction to Research (IMSE001/ELCE701)
  5. Thesis (ELCE799)

Ph.D. Courses

  1. Advanced Topics in Electrical and Computer Engineering (ELCE818)
  2. Microelectronics in Signal Processing and Communications (ELCE808)

Research

Research Interests

  • High-Performance Data Converters
            – Pipelined, SAR, Flash, Binary Search, etc…
            – Oversampling Data Converters
  • Analog Integrated Circuits for Artificial Intelligence
  • Power Management Integrate Circuits
  • Analog and Mixed-Signal Integrated Circuits

Thesis Co-Supervision

Ph.D. Thesis

  1. Present
Qi Liang, Low-Power Cascaded Delta-Sigma Modulator for
Wideband Telecommunication Applications
  1. Present
Dongyang Jiang, Advanced Techniques for CMOS Sigma-Delta Modulators
  1. Present
Mingqiang Guo, Advanced Techniques for CMOS Interleaved Data Converters
  1. Present
Biao Wang, Resolution Enhancement Techniques for Multi-Bit Incremental ADC
  1. 2018
Xing Dezhi, Advanced Techniques in Analog to Digital Converters
  1. 2018
Jianwei Liu, Design Techniques for Energy Efficient ADCs
  1. 2018
Feng Da, Polyphase Decomposition of Sigma-Delta A/D Converter
  1. 2017
Arshad Hussain, The Design of Passive Sigma-Delta ADC
  1. 2016
Zhong Jianyu, Design of High-Speed, Power-efficient SAR-Type ADCs
  1. 2015
Chi-Hang Chan, Design Techniques and Considerations in Low to Moderate to Low Resolution Power efficient GHz Range ADCs
  1. 2012
U-Fat Chio, Design Techniques for Low-Power High-Speed Analog-to-Digital Converters using Binary-Search and Subranging Schemes

 

M.Sc. Thesis

  1. Present
Haoyu Gong, High-Performance Sigma-Delta Converters
  1. Present
Qingyu Ma, High-Performance Sigma-Delta Converters
  1. Present
Cui Song, Digital Calibration Techniques for CMOS Pipelined Converters
  1. Present
Hanyu Wang, Digital Calibration Techniques for CMOS Pipelined Converters
  1. 2019
Jixuan Li, On the study of Battery Management System for Fast and High Efficiency Charging
  1. 2019
Hubert Liang, On the study of Programmable Continuous Time Sigma Delta Modulator for Implantable ECG Acquisition Circuit Application
  1. 2018
Jiaji Mao, Low Power Pipelined Analog-to-Digital Converter
  1. 2017
Qin Weiwei, Quick and Cost-efficient Measurement Techniques for High-performance A/D Converters 
  1. 2017
Yan Rongshen, On the Study of Advanced CMOS Operational Amplifiers
  1. 2016
Li Wei, On the Study of Mixed Signal Interface Circuit for Inertial Navigation System
  1. 2016
Ren Yuan, On the study of High DR Multi-Channel Stage-Shared Hybrid Front-End for Integrated Power Electronics Controller
  1. 2013
Yun Du, High-Performance Continuous-Time Sigma-Delta Modulator 
  1. 2015
Yuan Fei, A 10b Pipelined ADC with Nonlinear Digital Background Calibration & 2.5b/stage Opamp Sharing Architecture
  1. 2013
Wenlan Wu, Monotonic Multi-Switching Method for Ultra-Low-Voltage Energy Efficient SAR ADCs 
  1. 2013
Cheok-Teng Lei, Applying the Novel High Speed Robust Level Converter to a 12-bit Successive Approximation Analog-to-Digital Converters with Dual Supply Domain
  1. 2013
Cai Chenyan, Low Power High Efficiency Excess-Loop-Delay Compensation Techniques in Continuous-Time Delta-Sigma Modulators
  1. 2012
Jiang Yang, On the Study of Clock-Jitter Insensitive Circuit Techniques in Continuous-Time Sigma-Delta Modulators
  1. 2012
Peng Zhang, 时间交织型模数转换器时钟偏差校准技术研究(Joint-Supervision with Tsinghua University)
  1. 2012
Zhijie Chen, 应用于生物医学领域的ΣΔ调制器低功耗研究(Joint-Supervision with Tsinghua University)
  1. 2012
Rui Wang, 基于数字校准的流水线逐次逼近模数转换器的芯片实现 (Joint-Supervision with Tsinghua University)
  1. 2011
Guohe Yin, 满足生物医学低功耗需求的模数转换器设计技术研究 (Joint-Supervision with Tsinghua University)
  1. 2011
Chi-Hang Chan, A Study on Comparator and Offset Calibration Techniques in High Speed Nyquist ADCs
  1. 2011
Si-Seng Wong, Design of Analog-to-Digital Converters with Binary Search Algorithm and Digital Calibration Techniques
  1. 2010
Li Ding, Comprehensive Digital Calibration Techniques For High Resolution ADCs
  1. 2010
Kim-Fai Wong, Speed Enhancement Techniques for Comparator-Based Switched-Capacitor Circuits

 

Bachelor Thesis (16 Projects, 29 B.Sc students)

  1. 2018
Lo Kit Chon, Cheok Ka Hou, A 10b 100MS/s Pipeline Analog-to-Digital Converter
  1. 2017
Leong Hoi Chon, Lam Sao Son, High Performance Pipelined Analog-to-Digital Converter
  1. 2017
Chu Meng Lok, Low quiescent current power management
  1. 2016
Wang Linxuan, Mao Xinwei, Cui Song, Bandwidth mismatch calibration techniques for wideband time-interleaved pipelined analog-to-digital converters
  1. 2014
Jiang Dongyang, Liang Junhao, A 107 dB DR, 106dB SNDR Sigma-Delta ADC Using a Charge-Pump Integrator for Audio Application
  1. 2014
Li Ji Xuan, Zeng Wen Liang, Power Efficient and Fast Charger Techniques Applied for Battery Management System
  1. 2013
Fong Tek Kei, A 103dB Dynamic Range, 106dB SNDR Sigma-Delta ADC for Audio Applications
  1. 2013
Bai Ziwen, A Micropower Management System for Photovoltaic Cells with Maximum Output Power Control
  1. 2012
Zhou Tianxiang, A Multibit Dual-Feedback CT Sigma Delta Modulator with Lowpass Signal Transfer Function
  1. 2012
Cheng Xiaojing, Ding Shixuan, Wideband Time-Interleaved Pipelined ADC using LMS Timing-Skew Calibration Engine for a 4G LTE Smartphone
  1. 2011
Yan Pengyu, Chen Zhiyuan, A 13-bit 64 MS/s Digital Enhanced Pipelined ADC for 4G LTE Application
  1. 2010
Du Yun, He Tao, A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator with VCO-Based Quantizer for WiMAX Application
  1. 2009
Jiang Yang, Yu Xiaofeng, Cai Chenyan, A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers
  1. 2009
Fan Wa Pan, Chio Chan Keong, A 1-V 12-bit 200-MS/s Pipelined ADC with Digital Signal-Dependant Dithering Calibration for HDTV Video Analog Frond-End
  1. 2008
Chon-Hei Lei, Background Digital Calibration for Full HD(High-Definition) Video Analog Front-End
  1. 2008
Sio Chan and Li Ding, Low-Power High-Speed Comparator-Based Pipeline ADC for Portable Wireless Devices
  1. 2008
Wai-Hou Chan and Li Xie, A 10-bit 60-MS/s Asynchronous Charge-Sharing SAR ADC in 90-nm CMOS for Mobile TV Applications
  1. 2008
Yin-Sheng Zhao and Seng-Cheong Chao, Comparator-Based Multi-mode Sigma Delta Modulator for 3G Analog Front-End
  1. 2008
Po-Lap Chan and Ka-Cheong Lao, Study of Low Drop-Out Regulators for Power Management in Portable Devices

Funded Research Projects

  • Principal Investigator, “Study of Background Calibration Techniques of Split-Type Analog-to-Digital Converters with Nested and Parallel Split ADC Calibration,” Multi-Year Research Grant, funded by Research Committee of University, 2019 – 2021.
  • Principal Investigator, “Research of Power Efficient Wideband Oversampling Delta-Sigma Modulator ADCs,” funded by Macau Science and Technology Development Fund, 2018 – 2020.
  • Principal Investigator, “Mismatch- and Supply-Noise-Tolerant Design for Wideband Nyquist Analog-to-Digital Conversion Integrated Circuits,” Multi-Year Research Grant, funded by Research Committee of University, 2018 – 2020.
  • Member, “Research on mm-size Extremely Power-Constrained Implantable ECG System on Chip Design,” Jointly-funded by Macau Science and Technology Development Fund & National Science Foundation Committee, China (FDCT-NSFC), 2017 – 2019.
  • Principal Investigator, “High-Performance Wideband Data Conversion Interfaces for an Evolving Informative World,” funded by Macau Science and Technology Development Fund & Match-Fund from RC, UM, 2014 – 2016.
  • Co-Principal Investigator, “ASIANS – Advances on Sensor Inertial Aided Navigation Systems,” Multi-Year Research Grant, funded by Research Committee of University, 2012 – 2015.
  • Principal Investigator, “Support in Establishment of State Key Laboratory of Analog and Mixed-Signal VLSI (Data Conversion and Signal Processing Research Line),” funded by Macau Science and Technology Development Fund, 2011 – 2013.
  • Principal Investigator, “Research and Development of Comprehensive Data Conversion Platforms in Nanometer CMOS Technology,” funded by Macau Science and Technology Development Fund, 2010 – 2012.
  • Principal Investigator, “Research and Development of Comprehensive Data Conversion Platforms in Nanometer CMOS Technology,” Match-Fund, funded by Research Committee of University, 2010 – 2012.
  • Co-Principal Investigator, “Integrated generalized PWM controller for DC-AC inverter,” funded by Macau Science and Technology Development Fund, 2010 – 2012.
  • Co-Principal Investigator, “Integrated generalized PWM controller for DC-AC inverter,” Match-Fund, funded by Research Committee of University, 2010 – 2012.
  • Co-Principal Investigator, “High-Speed, High-Resolution, Low-Power Analog-to-Digital Conversion System with Emerging Scaled CMOS Technology,” funded by Macau Science and Technology Development Fund, 2007 – 2009.
  • Co-Principal Investigator, “High-Speed, High-Resolution, Low-Power Analog-to-Digital Conversion System with Emerging Scaled CMOS Technology,” Match-Fund, funded by Research Committee of University, 2007 – 2009.

Industrial Engineering Projects

  • Advanced IC project developed in the area of high-performance DC-DC Converter, in collaboration with Allwinner, China.
  • Advanced IC project developed in the area of high-performance Analog-to-Digital Converter, in collaboration with Hisilicon-Huawei, China.

Professional Services – External

2013 – Present Technical Program Committee Member, The IEEE Asian Solid-State Circuits Conference (A-SSCC)
2013 – Present Student Design Contest Committee Member, The IEEE Asian Solid-State Circuits Conference (A-SSCC)
2019 – Present Chair of Award Committee, The IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)
2018 – Present Chair of Analog Mixed-Signal IC TPC Sub-Committee, The IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)
2017 Chair of RCM Review Committee, The IEEE International Symposium on Circuits and Systems (ISCAS)
2016 Publication Chair, The IEEE Asian South Pacific Design Automation Conference (ASPDAC)
2015 Track Chair, The IEEE TENCON Conference
2015 Review Track Chair, The IEEE TENCON Conference
2015 Technical Program Committee Member, The IEEE VLSI-SoC Conference
2015 Technical Program Committee Member, The IEEE International Wireless Symposium Conference
2015 Technical Program Committee Member, The IEEE ASICON Conference
2011 – 2012 Technical Program Committee Member, The IEEE Radio Frequency Integration Technology Conference (RFIT)
2012 Ph.D Defense Examination Committee Member (External), The New University of Lisbon, Lisboa, Portugal
2011 Technical Program Committee Member, The IEEE Sensors 2011 Conference
2009 – Present Secretary, IEEE Solid-State Circuit Society (SSCS) Macau Chapter.
2009 – Present Treasurer/Secretary, IEEE Macau CAS/COM Joint Chapter.
2009 Review Committee Member (RCM), The 2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)
Dec 2008 Special-Session Co-Chair & Local Organization Member, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2008, Macau, China.
Jul 2008 Referee Committee, 2008 Macau’s High-School Student Funny Science Competition, Macau, China
Jul 2006 Technical Session Chair, the Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC), 2006, Macau, China
Dec 2004 Financial Committee Co-Chair & Technical Session Co-Chair, 2004 IEEE/IEEJ (7th) International Analog VLSI Workshop, Macau, China

Professional Services – Internal

Jul 2017 – Present

Coordinator, Data and Power Conversion (DP) Research Centre, State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau

2017 Dec

Chair, Academic Promotion Ad-hoc Committee, AMSV, University of Macau

2017 Nov

Member, Panel of ECE Principals’ Recommended Admission, ECE,FST, University of Macau

2016 Sept – Present

Academic-in-charge of UM-Temple 3+2 program, ECE,FST, University of Macau

2017 Dec – Present

Vice-Coordinator of UM-IST 3+2 program, ECE,FST, University of Macau

2016 Jan – Present

Coordinator of UM UG Reform – ECE program, ECE,FST, University of Macau

2012 Sept – Present

Chair, Program Revision Committee, ECE,FST, University of Macau

2012 – Present

Member, Department Executive CommitteeECE,FST, University of Macau

2012 Sept – 2013 Aug

Member, Program Accreditation Committee, ECE,FST, University of Macau

Sep 2007 – Jul 2017

Coordinator, Data Conversion and Signal Processing (DCSP) Research Line, State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau

Sep 2007 – Jul 2017

Co-Coordinator, Integrated Power Research Line, State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau

2011 – 2012 Aug

Member of Board of Examiner, ECE, FST, University of Macau

2010 – Present

PhD Thesis Proposal Assessment Committee Member, FST, University of Macau

2010 – Present

PhD Qualifying Examination Committee Member, FST, University of Macau

2009 – 2010

Member of Establishment Task Force, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau

2009 – 2011

Mentor, FST, University of Macau

2009 – Present

Member of Academic Council, FST, University of Macau.


University Student Life and Development Service

2017 Sept – Present

College Fellow,Shiu Pong College,University of Macau

2015 Sept – 2017 Aug

College Affiliate,Shiu Pong College,University of Macau

2012 Sept – Present

Student Advisory Program for course enrollment


Professional Review Services

  • Journal
    • IEEE Journal of Solid-State Circuits
    • IEEE Transactions on Circuits and Systems I – Regular Papers
    • IEEE Transactions on Circuits and Systems II – Express Briefs
    • IEEE Transactions on VLSI Systems
    • IEEE Transactions on Instrumentation and Measurement
    • Journal of Circuits, Systems and Computers
    • International Journal of Circuit Theory and Applications
  • Conferences
    • IEEE International Symposium on Circuits and Systems (ISCAS)
    • IEEE Biomedical Circuits and Systems Conference (BIOCAS)
    • IEEE Conference on Postgraduate Research in Microelectronics & Electronics (PRIME)
    • IEEE Conference on Asia-Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

Honors and Awards

2018 Awardee of Incentive Award Scheme for Outstanding Academic Staff 2017/2018, University of Macau
2016 Co-recipient of Third Class, Macau Scientific and Technological Invention Award  澳門科學技術發明獎三等獎
2014 Co-recipient of Second Class, Macau Scientific and Technological Invention Award  澳門科學技術發明獎二等獎
2012 Co-recipient of Second Class, Macau Scientific and Technological Invention Award  澳門科學技術發明獎二等獎
2012 Co-recipient of Macau Scientific and Technological Special Award  澳門科學技術特別獎勵
2011 (First-time in Macau) Co-recipient of Second Class, State Scientific and Technological Progress Award  (澳門首獲)國家科學技術進步獎二等獎
Nov 2008 Chipidea Microelectronics Prize – Postgraduate Level, for the outstanding academic and research achievement in Microelectronics.(organized by University of Macau)
Jul 2006 Paper with Certificate of Merit, Regional Inter-University Post-graduate Electrical and Electronic Engineering ConferenceIEEE RIUPEEEC’2006.
May 2005 Student Paper Contest Award, International Symposium on Circuits and Systems (ISCAS’2005):

Student Honors and Awards under Advisory

Jun 2017 IEEE CASS Scholarship, 2017 IEEE PRIME Conference
Mingqiang Guo, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Split-based time-interleaved ADC with digital background timing-skew calibration,” in IEEE Ph.D Research in Micro-electronics & Electronics (PRIME), Jun 2017.
Oct 2016 1 students win 2016 Postgraduate Science and Technology Research and Development Award (FDCT)
Jun 2016 Silver Leaf Certificate, 2016 IEEE PRIME Conference
Biao Wang, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A high resolution multi-bit incremental converter insensitive to DAC mismatch error,” in IEEE Ph.D Research in Micro-electronics & Electronics (PRIME), Jun 2016.
Feb 2015 1 student win 2015 IEEE SSCS Pre-Doctoral Achievement Award
Oct 2014 2 students win 2016 Postgraduate Science and Technology Research and Development Award (FDCT)
Nov 2012 4 students win 2012 Postgraduate Science and Technology Research and Development Award (FDCT)
Jun 2012 2012 Best Master Thesis Award in Tsinghua University
By Guohe Yin, 满足生物医学低功耗需求的模数转换器设计技术研究 (Joint-Supervision with Tsinghua University)
Jun 2012 Travel Grant Award, 2012 IEEE Symposium on VLSI Circuits, Hawaii
Paper: Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, and R. P. Martins, “A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure”
Nov 2011 Student Design Contest Award, IEEE 2011 Asian Solid-State Circuits Conference (A-SSCC)
Paper: Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R.P.Martins, Franco Maloberti, “A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation”
Feb 2011 Silk Road Paper Award, IEEE 2011 Internal Solid-State Circuits Conference (ISSCC)
Paper: He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins and F. Maloberti, “A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS”
Jun 2012 2nd Runner-upfor the Final Year Project Supervised: Zhao Tianxiang, “A Multibit Dual-Feedback CT Sigma Delta Modulator with Lowpass Signal Transfer Function,” 2012 IEEE Project Competition, Macau
Nov 2009 Third Prizefor the Final Year Project Supervised: Jiang Yang, Yu Xiaofeng, Cai Chenyan, “A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers,” “Challenge Cup” National Intervarsity Science and Technology Competition, China
Sep 2009 Bronze Leaf Certificate, 2009 IEEE PrimeAsia Conference
U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Si-Seng Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Comparator-Based Successive Folding ADC,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pp. 117-120, Nov. 2009.
Sep 2009 Championfor the Final Year Project Supervised: Jiang Yang, Yu Xiaofeng, Cai Chenyan, “A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers,” 2009 IEEE Project Competitions, Macau
Sep 2008 Championfor the Final Year Project Supervised: Li Ding, Sio Chan, “A Pseudo-Differential Comparator-Based Pipelined ADC,” 2008 IEEE Project Competitions, Macau
Sep 2008 1st Runner-Upfor the Final Year Project Supervised: Lei Chon Hei, “A Pseudo-Differential Comparator-Based Pipelined ADC,” 2008 IEEE Project Competitions, Macau
Jun 2008 1st Runner-up – Undergraduate Section for the Final Year Project Supervised: Li Ding, Sio Chan, “A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique,” IET Young Members Exhibition and Conference 2008, organized by Young members Section, IET(HK), Hong Kong, China

Invited Talks

  1. “Design Techniques for Nanometer CMOS Analog-to-Digital Converters” Huazhong University of Science and Technology, Jul 2019.
  2. Opening Remark in Advanced IC Summer Course in Zhuhai, Jul 2019.
  3. “The Design of High Spectral Purity Data Converters – from High-Resolution Oversampling to Wideband Nyquist” SKL Workshop, Dongguan, China, Apr 2019.
  4. “The Design of High Linearity Multi-bit Continuous-Time Sigma-Delta Modulator” ICAC (华人芯片设计技术研讨会) Apr 2019.
  5. “Design Techniques for Nanometer CMOS Analog-to-Digital Converters” 物聯網與固態電路國際論壇, Hsingzhu, Taiwan, China, Nov 2018.
  6. “Design Techniques for Nanometer CMOS Analog-to-Digital Converters” University of Electronics, Science and Technology, Chengdu, China, Sept 2018.
  7.  “智能設備與智能生活” – Shiu Pong RC College, UM, Mar. 2018.
  8.  “智能設備與智能生活” – 培道中學科普講座 , Sept. 2017.
  9. “升學之路座談” – 同善堂中學科普講座 , Jan. 2017.
  10.  “Design Techniques for Nanometer Data Converters,” University of Porto, Porto, Portugal, Jun. 2016.
  11. “Energy Efficient SAR-Type ADCs, Part II – Practical Design Case Study,” Tutorial Speaker, International Symposium on Integrated Circuits (ISIC), Singapore, Dec. 2014.
  12.  “Design Techniques for Nanometer Data Converters,” Invited Speaker, CMOSET 2014 Dec. Grenoble, France, Jul 2014.
  13.  “Macao Chip by Macao People” – Sharing Session on the First State Scientific and Technological Progress Award for Macao澳門人, 澳門” – 澳門首獲國家科學技術進步獎成果分享, Feb. 2012.
  14. “Research and Future Perspective of Data Converters Research”, Academic Committee Meeting, State-Key Laboratory of Analog and Mixed-Signal VLSI, Mar. 2012.
  15.  “Design Techniques for Nanometer Data Converters,” Institute of Superior Technico (IST), Lisboa, Portugal, Mar. 2012.
  16.  “Design Techniques for Nanometer Data Converters,” The New University of Lisbon, Lisboa, Portugal, Mar. 2012.
  17. “High-Speed, High-Resolution, Low-Power Analog-to-Digital Conversion System with Emerging Scaled CMOS Technology”, FDCT Project Presentation, Macau Science and Technology Development Fund, Nov. 2011.
  18.  “Design Techniques for Nanometer Data Converters,” Hong Kong University of Science and Technology, Hong Kong, Dec. 2010.
  19. “Macau Microelectronics Development – Histories and Prospects” University of Macau, Macau, Oct. 2009 and Nov 2010.
  20.  “Introduction to the Research in Data Conversion and Signal Processing Research Line at University of Macau,” Tsinghua University, Shenzhen, Nov 2009.
  21.  “Introduction to the Research in Data Conversion and Signal Processing Research Line at University of Macau,” Fudan University, Shanghai, May 2009.

Scientific Publications

Book

  1. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters, Analog Circuits and Signal Processing, Springer,  Oct. 2010.
    Printed version:     (ISBN: 978-90-481-9709-5)
    e-Book:   (ISBN: 978-90-481-9710-1)
    Link: http://www.springer.com/engineering/electronics/book/978-90-481-9709-5

Patents

  1. Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Martins, “Limit cycle oscillation reduction technique for digital low dropout regulators,” US Patent in press.
  2. Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, R.P.Martins, F.Maloberti, “Time-Interleaved Pipelined-SAR Analog to Digital Converter with Low  Power Consumption,” US Patent, No. 8,427,355, from 23rd Apr, 2013.
  3. Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, R.P.Martins, F.Maloberti, “Analog to Digital Converter Circuit(類比至數位轉換器電路),” Taiwan Patent, No. 201242261, Mar 2014.
  4. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P. Martins and Franco Maloberti, “N-Bits Successive Approximation Register Analog-to-Digital Converter Circuit,” US PatentNo: 8,344,931, from 1th Jan, 2013.
  5. He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Delay Generator,” US patent, No. US8,411,259 B2, May 2013.
  6. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins and Franco Maloberti, “Analog-to-Digital Converting System (類比數位轉換系統),” Taiwan Patent No: 100103984, 2011.
  7. He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Delay Generator (延遲產生器),” Taiwan Patent,  No. 201246793, Mar 2014.
  8. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins and Franco Maloberti, “Cascade Analog to Digital Converting System,” US Patent, No. 8,466,823 B2, 2nd Aug, 2012.
  9. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins “Comparator and Calibration Thereof,” US Patent, No. 13/675311, Jul 2014.

Journal Papers

IEEE Journal of Solid-State Circuits (JSSC)

  1. Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, R. P. Martins and Maurits Ortmanns, “A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance,” in press in IEEE Journal of Solid-State Circuits.
  2. U-Fat Chio, Kuo-Chih Wen, Sai-Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, R. P. Martins, An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery“, in press in IEEE Journal of Solid-State Circuits (Invited Special Issue of A-SSCC).
  3. Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins, A 550mW 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental SD ADC with 256 clock cycles in 65nm CMOS”, IEEE Journal of Solid-State Circuits, vol. 54, Issue 4, pp. 1161-1172 Apr 2019 (Invited Special Issue of VLSI).
  4. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, ” A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC “, IEEE Journal of Solid-State Circuits. vol. 51, Issue 2, pp. 365-377, Feb 2016.  
  5. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti, “A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS”, IEEE Journal of Solid-State Circuits. vol. 48, Issue 9, pp. 2154-2169, Sept 2013.  
  6. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC“, in IEEE Journal of Solid-State Circuits. vol. 48, Issue 8, pp. 1783-1794, Aug 2013.  (Invited Special Issue of CICC)
  7. He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti, “A 8-bit 400MS/s 2-bit per cycle SAR ADC with Resistive DAC”, IEEE Journal of Solid-State Circuits, vol. 47, Issue 11, pp. 2763-2772, Nov 2012.  
  8. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, “A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation“, IEEE Journal of Solid-State Circuits, vol. 47, Issue 11, pp. 2614 – 2626, Nov 2012.  
  9. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P. Martins and Franco Maloberti, ” A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111 – 1121, Jun 2010.

IEEE Transactions on Circuits and Systems I – Regular Papers (TCAS-I)

  1. Wen-Liang Zeng, Chi-Seng Lam, Sai-Weng Sin, Franco Maloberti, Man-Chung Wong, Rui Paulo Martins, “A 220-MHz Bondwire-Based Fully-Integrated KY Converter with Fast Transient Response under DCM Operation “, in IEEE Transactions on Circuits and Systems I – Regular Papers, vol.65, no. 11, pp3984-3995, Nov 2018.  
  2. Liang Qi, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins, “A 4.2mW 77.1dB-SNDR 5MHz-BW DT 2-1 MASH ΔΣ Modulator with Multirate Opamp Sharing “, in IEEE Transactions on Circuits and Systems I – Regular Papers, vol. 64, no. 10, pp. 2641-2654, Oct 2017.  
  3. Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC,” in IEEE Transactions on Circuits and Systems I – Regular Papers, vol. 64, no. 7, pp. 1684-1695, Jul 2017.  
  4. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R.P.Martins, Franco Maloberti, “A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC,” in IEEE Transactions on Circuits and Systems I – Regular Papers, vol. 64, no. 8, pp. 1966-1976, Aug 2017.  
  5. Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs,” in IEEE Transactions on Circuits and Systems I – Regular Papers, vol. 62, no. 9, pp. 2196-2206, Sep 2015.  
  6. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps,” in IEEE Transactions on Circuits and Systems I – Regular Papers, vol. 55, no. 8, pp. 2188-2201, Sep 2008.

IEEE Transactions on Circuits and Systems II – Express Briefs (TCAS-II)

  1. Da Feng, Edoardo Bonizzoni, Franco Maloberti, Sai-Weng Sin and R. P. Martins, “A 10-MHz Bandwidth Two-Path Third-Order SD Modulator with Cross-Coupling Branches” in IEEE Transactions on CAS – Part II: Express Briefs, vol.65, no. 10, pp1410-1414, Oct 2018.
  2. Jiaji Mao, Mingqiang Guo, Sai-Weng Sin and R. P. Martins, “A 14-bit Split-Pipeline ADC with Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current” in IEEE Transactions on CAS – Part II: Express Briefs, vol.65, no. 10, pp1380-1384, Oct 2018.
  3. Ya-Jie Wu, Chi-Seng Lam, Man-Chung Wong, Sai-Weng Sin and R. P. Martins, “A Reconfigurable and Extendable Digital Architecture for Mixed Signal Power Electronics Controller” in IEEE Transactions on CAS – Part II: Express Briefs, vol.65, no. 10, pp1480-1484, Oct 2018.
  4. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Boris Murmann, Seng-Pan U, R. P. Martins, “Metastablility in SAR ADCs” in IEEE Transactions on CAS – Part II: Express Briefs, vol.64, no. 2, pp111-115, Feb 2017.
  5. Yan Lu, Haojuan Dai, Mo Huang, Man-Kay Law, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “ A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting” in IEEE Transactions on CAS – Part II: Express Briefs, vol.64, no. 2, pp166-170, Feb 2017. .
  6. Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, Wing-Hung Ki, “Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators” in IEEE Transactions on CAS – Part II: Express Briefs, vol.63, no. 9, pp903-907, Sep 2016
  7. Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A Fully-Integrated Digital LDO with Coarse-Fine-Tuning and Burst-Mode Operation” in IEEE Transactions on CAS – Part II: Express Briefs, vol.63, no. 7, pp683-687, Jul 2016
  8. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti “Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC”in IEEE Transactions on CAS – Part II: Express Briefs, vol.57, issue8,pp607-611, Aug 2010
  9. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins and Franco Maloberti, “Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC,” in press in IEEE Trans. On Circuits and System II – Express Briefs, vol. 57, no. 8, pp. 607 – 611, Aug 2010
  10. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS,” in IEEE Trans. On Circuits and System II – Express Briefs, vol. 57, no. 1, pp. 16-20, Jan 2010.
  11. Sai-Weng Sin, U-Fat Chio, Seng-Pan U and R. P. Martins, “Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch,” in IEEE Trans. on Circuits and Systems II – Express Briefs, vol. 55, no. 7, pp. 648 – 652, Jul 2008.

IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)

  1. Da Feng, Franco Maloberti, Sai-Weng Sin, Rui Paulo Martins, “Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 5, Issue 4, pp. 537-547, Dec. 2015.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)

  1. Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 2, pp. 481 – 485, Feb 2019. 
  2. Arshad Hussain, Sai-Weng Sin, Chi-Hang Chan, Seng-Pan U, Franco Maloberti, Rui Paulo Martins, “Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications,” in in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 1, pp. 364 – 374, Jan 2017.   
  3. Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins, “Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 1168 – 1172, Mar 2017.
  4. Jianwei Liu, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 7, pp. 2603 – 2607, Jul 2016. 
  5. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti, “Split-SAR ADCs: Improved Linearity with Power and Speed Optimization in 90nm CMOS,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 372-383, Feb. 2014.

IEEE Transactions on Power Electronics (TPEL)

  1. Man-Chung Wong, Yan-Zheng Yang, Chi-Seng Lam, Wai-Hei Choi, Ning Yi Dai, Yajie Wu, Chi-Kong Wong, Sai-Weng Sin, U-Fat Chio, Seng-Pan, U, R.P.Martins, “Self-Reconfiguration Property of a Mixed Signal Controller for Improving Power Quality Compensation During Light Loading,” in IEEE Trans. on Power Electronics, vol. 30, no. 10, pp. 5938 – 5951, Oct 2014.

IEEE Transactions on Instrumentation and Measurement (TIM)

  1. Seng-Pan U, Sai-Weng Sin and R.P.Martins, “Exact spectra analysis of sampled signal with jitter-induced nonuniformly holding effects,” in IEEE Trans. on Instrumentation and Measurement, vol. 53, no. 4, pp. 1279 – 1288, Aug 2004.

Other Journals

  1. Y. J. Mao, Chi-Seng Lam, Sai-Weng Sin, Man-Chung Wong, Rui Paulo Martins, ” Review and Selection strategy for high accuracy modeling of PWM converters in DCM “, in Journal of Electrical and Computer Engineering, vol. 1, pp. 1-16, Oct. 2018.
  2. Wei Wei Qin, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “Quick and Cost-efficient A/D Converter Static Characterization Using Low-precision Testing Signal”, in Elsevier Microelectronics Journal, vol. 74, pp. 86-93, Apr 2018.
  3. Ziyang Luo, Yan Lu, Mo Huang, Junmin Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins,” A Sub-1V 78-nA Bandgap Reference with Curvature Compensation”, Elsevier Microelectronics Journal,vol. 63, Issue C, pp. 35-@, May. 2017.
  4. Dongyang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti, ” Reconfigurable mismatch-free time-interleaved bandpass sigma–delta modulator for wireless communications”, IET Electronics Letter, vol. 53, Issue 7, pp. 506-508, Mar. 2017.
  5. Yi-Wei Tan, Chi-Seng Lam, Sai-Weng Sin, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins, ” DCM Operation Analysis of 3-Level Boost Converters “, in IET Electronics Letter, vol. 53, Issue 4, pp. 270-272, Feb. 2017.
  6. Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan, U, R.P.Martins, ” A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS”, in Journal of Semiconductor Technology and Science, Vol. 16, No. 4, pp. 395-404, Aug 2016.
  7. Wen-Liang Zeng, Chi-Seng Lam, Wen-Ming Zheng, Sai-Weng Sin, Ning-Yi Dai, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins, ” DCM operation analysis of KY converter “, IET Electronics Letter, vol. 51, Issue 24, pp. 2037-2039, Nov. 2015.
  8. Qi Liang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, ” Resolution-enhanced sturdy MASH delta–sigma modulator for wideband low-voltage applications”, IET Electronics Letter, vol. 51, Issue 14, pp. 1061-1063, Jul. 2015.
  9. Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters”, Analog Integrated Circuits and Signal Processing, Springer, vol. 76, Issue 1, pp. 35-46, Jul. 2013.
  10. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, ” Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs,” in Hindawi VLSI Design, Special Issue “Selected Papers from the Midwest Symposium on Circuits and Systems”, vol. 2010, no. 1, pp. 1-8, Apr 2010.
  11. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 1.2-V 10-bit 60-360MS/s Time-Interleaved Pipelined ADC in 0.18um CMOS with Minimized Supply Headroom”, in IET Proceedings – Circuits, Devices and Systems,vol. 4, no. 1, pp. 1-13, Jan 2010.
  12. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18um CMOS”, 澳門機電工程專業協會(APEMEM)會刊(2007-2008), pp. 37-43.

Conference Papers

IEEE International Solid-State Circuit Conference (ISSCC)

  1. Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, R. P. Martins and Maurits Ortmanns, “A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28 nm CMOS,” in IEEE International Solid-State Circuit Conference (ISSCC) 2019, pp.336-337, Feb 2019.
  2. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A 5.5mW 6b 5GS/s 4-times Interleaved 3b/cycle SAR ADC in 65nm CMOS,” in IEEE International Solid-State Circuit Conference (ISSCC), pp.466-467, 2015.
  3. Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai-Weng Sin,  Seng-Pan U, R. P. Martins, “A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors,” in IEEE International Solid-State Circuit Conference (ISSCC), pp.364-365, 2015.
  4. He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins and F. Maloberti, “A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS,” in IEEE International Solid-State Circuit Conference (ISSCC), pp.188-189, Feb 2011. (ISSCC Silk Road Award)

IEEE International Symposium on VLSI Circuits (VLSI)

  1. Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, Hegong Wei, R.P.Martins, “A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing,” in 2019 Symposium on VLSI Circuits Digest of Technical Papers, Jun 2019(with Travel Grant Award).
  2. Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, R.P.Martins, “A 550mW 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS,” in 2018 Symposium on VLSI Circuits Digest of Technical Papers, pp. C76-C77, Jun 2018. (with Travel Grant Award, invited special issue in JSSC).
  3. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC,” 2012 Symposium on VLSI Circuits Digest of Technical Papers, page 90-91;13-15 June 2012, pp. 90-91, Jun 2012
  4. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure,” 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp. 86-87, Hawaii,Jun 2012. (with Travel Grant Award)

IEEE Custom Integrated Circuits Conference (CICC)

  1. Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, Hegong Wei, R.P.Martins, “A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration,” in Proc. of IEEE Custom Integrated Circuits Conference – CICC, Apr 2019 (invited special issue in JSSC).
  2. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC,” in Proc. of IEEE Custom Integrated Circuits Conference – CICC, Sept 2012 (invited special issue in JSSC).

IEEE European Solid-State Circuits Conference (ESSCIRC)

  1. Dante Gabriel Muratore, Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti, U-Fat Chio, Sai-Weng Sin, Rui Paulo Martins, “An 8-bit 0.7-GS/s Single Channel Flash-SAR ADC in 65-nm CMOS Technology “, in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2016, pp. 421-424, Sept 2016.
  2. Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction “, in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2016, pp. 169-172, Sept 2016.  
  3. Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, Rui Paulo Martins, ” A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique”, in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2012, Sept 2012.
  4. Guohe Yin, He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, Rui Paulo Martins, A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS “, in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2012, France, September 2012.
  5. U-Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, ” A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration”, in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC, pp. 363-366, Sept 2011.
  6. Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, R.P.Martins and F. Maloberti, “An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H”, in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC, pp. 218 – 221, Sept 2010.

IEEE Asian Solid-State Circuits Conference (A-SSCC)

  1. U-Fat Chio, Kuo-Chih Wen, Sai-Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, R. P. Martins, An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery“, IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp. 1-4, Nov 2018.
  2. U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, R.P.Martins, “A 5-bit 2 GS/s Binary-Search ADC with Charge-Steering Comparators“, IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp. 1-4, Nov 2017.
  3. Yuan Ren, Sai-Weng Sin, Chi-Seng Lam, Man-Chung Wong, Seng-Pan, U, R.P.Martins, ” A High DR Multi-Channel Stage-Shared Hybrid Front-End for Integrated Power Electronics Controller”, IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp. 1-4, Nov 2016.
  4. Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan, U, R.P.Martins, ” A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation”, IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp. 1-4, Nov 2015.
  5. Li Ding, Wenlan Wu, Sai-Weng Sin, Seng-Pan, U, R.P.Martins, ” A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration “, IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp. 77-80, Nov 2013
  6. Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC”, IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp. 153-156, Nov 2012
  7. Zhijie Chen, Yang Jiang, Chenyan Cai, He-Gong Wei, Sai-Wen Sin, Seng-Peng U, Zhihua Wang, R. P. Martins, “A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application”, IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp. 257-260, Nov 2012
  8. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R.P.Martins, Franco Maloberti, “A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation,” in IEEE Asian Solid-State Circuit Conference – A-SSCC, pp. 61-64, Nov 2011. (Student Design Contest Winner)
  9. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Reconfigurable Low-Noise Dynamic Comparator with Offset Calibration in 90nm CMOS,” in press in IEEE Asian Solid-State Circuit Conference – A-SSCC, pp. 233-236, Nov 2011.
  10. Si-Seng Wong, U-Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 4.8-bit ENOB 5-bit 500MS/s Binary-Search ADC with Minimized Number of Comparators,” in IEEE Asian Solid-State Circuit Conference – A-SSCC, pp. 73-76, Nov 2011.
  11. He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation,” in IEEE Asian Solid-State Circuit Conference (A-SSCC),  pp. 221-224, Nov, 2010.
  12. Sai-Weng Sin, He-Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R.P. Martins and Franco Maloberti, ” On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator,” in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC), pp. 49-52, Nov 2009.

IEEE International Symposium on Circuits and Systems (ISCAS)

  1. Yiwei Tan, Chi-Seng Lam, Sai-Weng Sin, Man-Chung Wong and R.P.Martins, ” Design and Control of An Integrated 3-Level Boost Converter under DCM Operation “, IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
  2. Da Feng, F.Maloberti, Sai-Weng Sin, Seng-Pan U and R.P.Martins, ” Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators “, IEEE International Symposium on Circuits and Systems (ISCAS),  May 2014.
  3. Wen-Lan Wu, Yan Zhu, U-Fat Chio, Li Ding, Chi-Hang Chan, Sai-Weng Sin,  Seng-Pan U,  Rui Paulo Martins, “A 0.6V 8b 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS”, IEEE International Symposium on Circuits and Systems (ISCAS),  May 2013.
  4. Yun Du, Tao He,  Yang Jiang, Sai-Weng Sin,  Seng-Pan U,  Rui Paulo Martins, “A Continuous-Time VCO-Assisted VCO-Based Sigma Delta Modulator with 76.6dB SNDR and 10MHz BW”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. May 2013.
  5. Tao He, Yang Jiang, Yun Du, Sai-Weng Sin, Seng-Pan U and Rui. P. Martins, “A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer,” in 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 65-69, May. 2012.
  6. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs”, in 2010 IEEE International Symposium on Circuits and Systems (ISCAS). pp. 607-611, May. 2010.
  7. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, “A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier”, in Proc. of 2008 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5-8, Seattle, USA, May 2008.
  8. Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits,” in Proceedings of 2006 IEEE International Symposium on Circuits and Systems – ISCAS’2006, p. 3794-3797, May 2006.
  9. Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Power-Efficient 1.056 GS/s Resolution-Switchable 5-bit/6-bit Flash ADC for UWB Applications,” in Proceedings of 2006 IEEE International Symposium on Circuits and Systems – ISCAS’2006, p. 4305-4308, May 2006.
  10. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems – ISCAS’2005,p. 1585-1588, May 2005.
  11. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems – ISCAS’2005,p. 1581-1584, May 2005.
  12. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, ” A Generalized Timing-Skew-Free, Multi-Phase Clock Generation Platform for Parallel Sampled-Data Systems,” in Proceedings of 2004 IEEE International Symposium on Circuits and Systems – ISCAS’2004, vol.1, pp. I-369 – I-372 , May 2004.
  13. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, ” Timing-Mismatch Analysis in High-Speed Analog Front-End with Nonuniformly Holding Output,” in Proceedings of IEEE International Symposium on Circuits and Systems 2003 – ISCAS’2003, vol. 1, pp. I-129 – I-132, May 2003.

IEEE International Conference on Acoustics, Speech & Signal Processing (ICASSP)

  1. Sai-Weng Sin, Seng-Pan U and R.P.Martins, “Quantitative Noise Analysis of Jitter-Induced Non-Uniformly Sampled-And-Held Signals,” in Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing – “ICASSP’2003″, vol. 6, pp. VI-253 – 256, April 2003.

IEEE International Solid-State CircuiIEEE Instrumentation and Measurement Technology Conference (IMTC)

  1. Seng-Pan U, Sai-Weng Sin and R.P.Martins, ” Spectra Analysis of Nonuniformly Holding Signals for Time-Interleaved Systems with Timing Mismatches,” in Proceedings of IEEE Instrumentation and Measurement Technology Conference – IMTC’2003, vol. 2, pp. 1298-1301, May 2003.

IEEE Midwest Symposium on Circuits and Systems (MWSCAS)

  1. Ding Li, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A Background Gain-Calibration Technique for Low Voltage Pipelined ADCs Based on Nonlinear Interpolation”, in press in IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2013.
  2. Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U and Rui. P. Martins, “An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1096 – 1099, Aug 2012.
  3. Zhong Jian Yu, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC”, IEEE Midwest Symposium on Circuits and Systems – MWSCAS, Aug. 2011
  4. Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U and Rui. P. Martins, “A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time ΣΔ Modulators,” IEEE Midwest Symposium on Circuits and Systems – MWSCAS, Aug. 2011.
  5. Yang Jiang, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “Clock-Jitter Sensitivity Reduction in CT ΣΔ Modulators Using Voltage-Crossing Detection DAC,” IEEE Midwest Symposium on Circuits and Systems – MWSCAS, Aug. 2011
  6. Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range,” IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Aug. 2011.
  7. Peng Zhang, Zhijie Chen, He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Zhihua Wang, “A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC,” IEEE Midwest Symposium on Circuits and Systems – MWSCAS, Aug. 2011.
  8. Zhijie Chen, Peng Zhang, Hegong Wei, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Zhihua Wang, “Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error,” IEEE Midwest Symposium on Circuits and Systems – MWSCAS, Aug. 2011.
  9. Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A Multi-Merged-Switched Redundant Capcitive DACs for 2b/cycle SAR ADC,” IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Aug 2011.
  10. Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Threshold-Embedded Offset Calibration Technique for Inverter-Based Flash ADCs,”  IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 489-492, Aug. 2010.
  11. Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Level-Shifting Variable Current Charging Technique for High-Speed Comparator-Based Switched-Capacitor Circuits,” Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 566-569, Aug. 2010.
  12. Si-Seng Wong, U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Power Effective 5-bit 600 MS/s Binary-Search ADC with Simplified Switching,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 29-32, Aug. 2010.
  13. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 889-892, Aug. 2010.
  14. Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U and R.P. Martins, ” A Modified Charging Algorithm for Comparator-Based Switched-Capacitor Circuits,” in Proc. of 2009 Midwest Symposium on Circuits and Systems (MWSCAS), pp. 86-89, Aug. 2009.
  15. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, ” Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs,” in Proc. of 2008 Midwest Symposium on Circuits and Systems (MWSCAS), pp. 922-925, Aug 2008.

IEEE International Conference on Electronics, Circuits and Systems (ICECS)

  1. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 547-550, Dec, 2010.
  2. Guohe Yin, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U, R.P. Martins, Zhihua Wang, “An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications” in Proc. of IEEE International Conference on Electronics, Circuits an d Systems (ICECS), pp. 878-881, Dec, 2010.
  3. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, “A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs,” in Proc. of 2008 IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 642-645, Aug 2008.

IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS)

  1. Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A Robust NTF Zero Optimization Technique for Both Low and High OSRs Sigma-Delta Modulators”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012, pp. 29-32, 2012
  2. Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity,”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012, pp. 33-36, 2012
  3. Wen-Lan Wu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array“, IEEE ASIA Pacific Conference on Circuits and system (APCCAS), 2012
  4. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1011-1014, Dec. 2010.
  5. Li Ding, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 208-211, Dec. 2010.
  6. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, ” A Process- and Temperature- insensitive Current-Controlled Delay Generator for Sampled-Data Systems,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1192-1195, Dec. 2008.
  7. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, ” A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1164-1167, Dec. 2008.
  8. Li Ding, Sio Chan, Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U and R.P. Martins, ” A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feed Forward Technique” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 276-279, Dec. 2008.

IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

  1. Seng-Pan U, Sai-Weng Sin, Yan Zhu, U-Fat Chio, He-Gong Wei and, R. P. Martins, ” Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs,” in Proc. of Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011, pp. 173-176, Nov 2011.

IEEE International SoC Design Conference (ISOCC)

  1. Arshad Hussain, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation,” in International SoC Design Conference – ISOCC, pp. 76-79, Nov 2011.
  2. Si-Seng Wong, Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs,in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 333-336, Nov. 2009.
  3. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins,A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator,in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 392-395, Nov. 2009.

Other International Conferences

  1. U. Chi-Wa, Chi-Seng Lam, Sai-Weng Sin, Man-Kay Law, Man-Chung Wong, Seng-Pan U, R.P.Martins, “CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression,” in 43rd Annual Conference of the IEEE Industrial Electronics Society (IECON), 2017.
  2. Xia Du, Chi-Seng Lam, Sai-Weng Sin, Man-Kay Law, Franco Maloberti, Man-Chung Wong, Seng-Pan U, R.P.Martins, “A digital pwm controlled ky step-up converter based on frequency domain ΣΔ ADC,” in 26th IEEE International Symposium on Industrial Electronics (ISIE 2017), Jun 2017.
  3. Xia Du, Chi-Seng Lam, Sai-Weng Sin, Franco Maloberti, Man-Chung Wong, Seng-Pan U, R.P.Martins, “A digital pwm controlled ky step-up converter based on passive sigma-delta modulator,” in The IEEE International Future Energy Electronics Conference 2017 – ECCE Asia (IFEEC 2017-ECCE Asia), Jun 2017.
  4. Mingqiang Guo, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Split-based time-interleaved ADC with digital background timing-skew calibration,” in IEEE Ph.D Research in Micro-electronics & Electronics (PRIME), Jun 2017.
  5. Wei Li, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Mixed-Signal Sigma-Delta Interface circuit for Navigation System Applications,” in International Symposium on Integrated Circuits, Dec 2016.
  6. Biao Wang, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A high resolution multi-bit incremental converter insensitive to DAC mismatch error,” in IEEE Ph.D Research in Micro-electronics & Electronics (PRIME), Jun 2016.
  7. Haojuan Dai, Yan Lu, Man-Kay Law, Sai-Weng Sin, Seng-Pan, U, R.P.Martins, “A review and design of the on-chip rectifiers for RF energy harvesting,” in IEEE International Wireless Symposium, Mar 2015.
  8. Da Feng, Sai-Weng Sin, E. Bonizzoni, F.Maloberti, “Time interleaved current steering DAC for ultra-high conversion rate,” in IEEE Ph.D Research in Micro-electronics & Electronics (PRIME), Jun 2014.
  9. Arshad Hussain, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “NTF Zero Compensation Technique For Passive Sigma-Delta Modulator,” in IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 82-85, Oct 2011.
  10. Yuan Fei, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Nonlinearity Digital Background Calibration Algorithm for 2.5bit/stage Pipelined ADCs With Opamp Sharing Architecture,” in IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 1-4, Oct 2011.
  11. Rui Wang, U-Fat Chio, Chi-Hang Chan, Li Ding, Sai-Weng Sin, Seng-Pan U, Zhihua Wang and R. P. Martins, “A time-efficient dither-injection scheme for pipelined SAR ADC,” in IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 9-12, Oct 2011.
  12. Bo Sun; U-Fat Chio; Chi-Seng Lam; Ning-Yi Dai; Man-Chung Wong; Chi-Kong Wong; Sai-Weng Sin; Seng-Pan U; R. P. Martins, “A FPGA-Based Power Electronics Controller for Hybrid Active Power Filters,” in IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 25-28, Oct 2011.
  13. Bo Sun; Ning-Yi Dai; U-Fat Chio; Man-Chung Wong; Chi-Kong Wong; Sai-Weng Sin; Seng-Pan U; R. P. Martins, “FPGA-based Decoupled Double Synchronous Reference Frame PLL for Active Power Filters”, 2011 6th IEEE Conference on Industrial Electronics and Applications (ICIEA), pp. 2145 – 2150, 2011.
  14. Yuan Fei, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Digital Background Nonlinearity Calibration Algorithm for Pipelined ADCs,” IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 115-118, Sep 2010.
  15. Li Ding, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Noise-Insensitive Offset Calibration Technique for Time Interleaved SAR ADC”, accepted in2010 IEEE Latin-American Symposium on Circuits and Systems (LASCAS).
  16. Li Ding, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Background Amplifier Offset Calibration Technique for High Resolution Pipelined ADC”, in 2010 IEEE International NEWCAS Conference, pp. 41-44, Jun. 2010.
  17. U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Si-Seng Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Comparator-Based Successive Folding ADC,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pp. 117-120, Nov. 2009. (Bronze Leaf Certificate)
  18. Sai-Weng Sin, Seng-Pan U and R.P.Martins, “Novel Timing-Skew-Insensitive, Multi-phase Clock Generation Scheme for Parallel DAC and N-Path Filter”, in Proceedings of RIUPEEEC, pp.133-136, Macao, China, July 2006. (Paper with Certificate of Merit)
  19. Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “A 1.8V 1.056GS/s 6-b Flash-Interpolation ADC for MB-OFDM UWB Applications”, in Proceedings of RIUPEEEC, pp.105-108, Macao, China, July 2006.
  20. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Novel Low-Voltage Circuit Techniques for Fully-Differential Reset- and Switched-Opamps,” in Proceedings of PRIME’2005,vol. 2, p. 398-401,  July 2005.
  21. Sai-Weng Sin, Seng-Pan U and R.P.Martins, “Novel low jitter multi-phase clock generation scheme for parallel analog-to-digital conversion systems,”in Proceedings of 2004 IEEJ International Analog VLSI  Workshop, vol.1, pp. 172 – 175 , Oct 2004.
  22. Sin Sai Weng, Lai Keng Chong, Chiang Kuok Vai, Choi Wai Wa, K.W.Tam and R.P.Martins, “An analytical linearization method for CMOS MMIC power amplifier using Multiple Gated Transistors,” in Proceedings of IEEE International Conference on ASIC – ASICON’2001, pp.670-672, Oct. 2001.
  23. Sin Sai Weng, Lai Keng Chong, Chiang Kuok Vai, Choi Wai Wa, K. W. Tam and R. P. Martins, “A New IMD3 Reduction Approach based on Composite Effect of g”m and g”ds,” in Proceedings of IEEE CAS Workshop on Wireless Communications and Networking, South Bend, Indiana, USA, Aug., 2001.

Professional Affiliations

  • Senior Member, The Institute of Electrical and Electronics Engineers (IEEE)

Contact Details

State-Key Laboratory of Analog and Mixed-Signal VLSI
University of Macau, N21
Avenida da Universidade, Taipa,
Macau, China

Room: N21-3007
Telephone: (853) 8822-8795
Fax: (853) 8397-8797
Email: terryssw